RF9340资料

0Typical Applications•3V Quad-Band GSM Handsets•Commercial and Consumer Systems•Portable Battery-Powered EquipmentProduct Description

The RF9340 is a high-power, high-efficiency power ampli-fier module with integrated power control. The device isself-contained with 50Ω input and output terminals. Thepower control function is also incorporated, eliminatingthe need for directional couplers, detector diodes, powercontrol ASICs and other power control circuitry; thisallows the module to be driven directly from the DAC out-put. The device is designed for use as the final RF ampli-fier in EGSM900, DCS and PCS handheld digital cellularequipment and other applications in the 880MHz to915MHz, 1710MHz to 1785MHz and 1850MHz to1910MHz bands. On-board power control provides over50dB of control range with an analog voltage input; and,power down with a logic “low” for standby operation.

9.600 TYP8.800 TYP8.200 TYP7.400 TYP6.800 TYP6.000 TYP5.400 TYP4.600 TYP4.000 TYP3.200 TYP2.600 TYP1.800 TYP1.200 TYP0.400 TYP0.0009.098 TYP0.0001.7978.2058.280TRI-BAND GSM900/DCS/PCS

POWER AMP MODULE

•EGSM900/DCS/PCS Products•GPRS Class 12 Compatible•Power StarTM Module

5.400 TYP6.000 TYP6.800 TYP7.400 TYP8.200 TYP8.275 TYP8.800 TYP9.600 TYPPin 18.7470.400 TYP1.200 TYP1.800 TYP2.600 TYP3.200 TYP4.000 TYP4.600 TYP5.92.0751.2450.306Pin 11.701.4510.00± 0.1010.00 ± 0.100.450± 0.075Optimum Technology Matching® Applied

Si BJTSi Bi-CMOSInGaP/HBT

9GaAs HBT

SiGe HBT

Package Style: Module (10mmx10mm)

GaN HEMT

9Si CMOS

GaAs MESFETSiGe Bi-CMOS

Features

•Complete Power Control Solution•Single 3.0V to 5.5V Supply Voltage•+34.7dBm GSM Output Power at 3.5V•+32.7dBm DCS/PCS Output Power at 3.5V

•58% GSM and 50% DCS/PCS ηEFF

VCC212DCS/PCS IN1BAND SELECT2TX ENABLE3VBATT4VREG5VRAMP6GSM900 IN78VCC29GSM900 OUT10VCC OUT11DCS/PCS OUT

Ordering Information

RF9340Tri-Band GSM900/DCS/PCS Power Amp ModuleRF9340 Power Amp Module 5-Piece Sample PackRF9340PCBA-41XFully Assembled Evaluation BoardRF Micro Devices, Inc.7628 Thorndike Road

Greensboro, NC 27409, USA

Tel (336) 6 1233Fax (336) 6 04http://www.rfmd.com

Functional Block Diagram

Rev A1 0507192-491

RF9340

Absolute Maximum Ratings

Parameter

Supply Voltage

Power Control Voltage (VRAMP)Input RF PowerMax Duty CycleOutput Load VSWR

Operating Case TemperatureStorage Temperature

Rating

-0.3 to +6.0-0.3 to +1.8

+8.55010:1-20 to +85-55 to +150

Unit

VDCVdBm%°C°C

Caution! ESD sensitive device.

RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s).

Parameter

Overall Power Control VRAMP

Power Control “ON”Power Control “OFF”

VRAMP Input CapacitanceVRAMP Input CurrentTurn On/Off Time

SpecificationMin.Typ.Max.

UnitCondition

0.2

15

1.50.2520102VVpFµAµsVVµAmAVmAµAVVµAVVµAdB

Max. POUT, Voltage supplied to the inputMin. POUT, Voltage supplied to the inputDC to 2MHz

VRAMP=VRAMP MAX

VRAMP=0.2V to VRAMP MAX Specifications

Nominal operating limits

PIN<-30dBm, TX Enable=Low, Temp=-20°C to +85°C

VRAMP=0.2V, TX Enable=HighTX Enable=HighTX Enable=Low

Overall Power Supply

Power Supply Voltage

3.0

Power Supply Current

13.5

5.5101502.98

VREG VoltageVREG Current

2.7

2.871002.02002.0155

Overall Control Signals

Band Select “Low”Band Select “High”

Band Select “High” CurrentTX Enable “Low”TX Enable “High”

TX Enable “High” Current

01.901.9

0.53.0500.53.02

Power Control VRAMP

Power Control Range

Note: VRAMP MAX=3/8*VBATT+0.18<1.5VVRAMP=0.2V to VRAMP MAX

2-492Rev A1 050719

RF9340

Parameter

Overall (GSM900 Mode)

Operating Frequency RangeMaximum Output Power

880 to 915+35.2+33.055+3-86.0-84.0

Forward Isolation 1-35Forward Isolation 2-25Cross Band Isolation 2f0 -24Second Harmonic-15Third Harmonic-30.0All Other

Non-Harmonic SpuriousInput Impedance50Input VSWR

Output Load VSWR Stability8:1Output Load VSWR Ruggedness10:1Output Load Impedance

5050

-80.0-82.5-25

-10-20-5-8.5-36

MHzdBmdBm%dBmdBmdBmdBmdBmdBmdBmdBmdBmΩ

3.5:1

VRAMP=0.2V to VRAMP MAX

Spurious<-36dBm, RBW=3MHz

Set VRAMP where VRAMP<34.2dBm into 50Ω load

Load impedance presented at RF OUT padVRAMP=0.2V to VRAMP MAX

SpecificationMin.Typ.Max.

UnitCondition

Temp=+25°C, VBATT=3.5V,

VRAMP=VRAMP MAX, VREG=2.8V, Freq=880MHz to 915MHz,

25% Duty Cycle, Pulse Width=11µs

+34.5+32.5

Total EfficiencyInput Power RangeOutput Noise Power

460

Temp = 25°C, VBATT=3.5V, VRAMP=VRAMP MAX

Temp=+85°C, VBATT=3.1V, VRAMP =VRAMP MAX

At POUT MAX, VBATT=3.5V

Maximum output power guaranteed at mini-mum drive level

RBW=100kHz, 925MHz to 935MHz, POUT > +5dBmRBW=100kHz, 935MHz to 960MHz, POUT > +5dBmTXEnable=Low, 0V, PIN=+5dBm

TXEnable=High, VRAMP=0.2V, PIN=+5dBmVRAMP=0.2V to VRAMP MAX VRAMP=0.2V to VRAMP MAX VRAMP=0.2V to VRAMP MAX VRAMP=0.2V to VRAMP MAX

ΩdB

Power Control VRAMP

Power Control Range

Note: VRAMP MAX=3/8*VBATT+0.18<1.5VRev A1 0507192-493

RF9340

Parameter

Overall (DCS Mode)

Operating Frequency RangeMaximum Output Power

1710 to 1785

+32.7

+31.052+3-85-40-20-15-30.0

-80-30-10-7-8.5-36

MHzdBmdBm%dBmdBmdBmdBmdBmdBmdBmΩ

3.5:1

VRAMP=0.2V to VRAMP MAX

Spurious<-36dBm, RBW=3MHz

Set VRAMP where VRAMP<34.2dBm into 50Ω load

Load impedance presented at RF OUT pinVRAMP=0.2V to VRAMP MAX, PIN=+5dBm

SpecificationMin.Typ.Max.

UnitCondition

Temp=25°C, VBATT=3.5V,

VRAMP=VRAMP MAX,

VREG=2.8V, Freq=1710MHz to 1785MHz, 25% Duty Cycle, pulse width=11µs

+31.8+30.0

Total EfficiencyInput Power RangeOutput Noise PowerForward Isolation 1Forward Isolation 2

Second HarmonicThird HarmonicAll Other

Non-Harmonic SpuriousInput ImpedanceInput VSWR

Output Load VSWR Stability

Output Load VSWR RuggednessOutput Load Impedance

440

Temp=25°C, VBATT=3.5V, VRAMP =VRAMP MAX

Temp=+85°C, VBATT=3.1V, VRAMP=VRAMP MAX

At POUT MAX, VBATT=3.5V

Maximum output power guaranteed at mini-mum drive level

RBW=100kHz, 1805MHz to 1880MHz, POUT > 0dBm, VBATT=3.5V

TXEnable=Low, 0V, PIN=+5dBm

TXEnable=High, VRAMP=0.2V, PIN=0dBm to +5dBm

VRAMP=0.2V to VRAMP MAX VRAMP=0.2V to VRAMP MAX VRAMP=0.2V to VRAMP MAX

50-8:110:1

5050

ΩdB

Power Control VRAMP

Power Control Range

Note: VRAMP MAX=3/8*VBATT+0.18<1.5V2-494Rev A1 050719

RF9340

Parameter

Overall (PCS Mode)

Operating Frequency RangeMaximum Output Power

1850 to 1910

+32.5

+30.850+3-85-40-20-15-30.0

-80-30-10-7-8.5-36

MHzdBmdBm%dBmdBmdBmdBmdBmdBmdBmΩ

3.5:1

VRAMP=0.2V to VRAMP MAX

Spurious<-36dBm, VRAMP=0.2V toVRAMP MAX, RBW=3MHz

Set VRAMP where VRAMP<34.2dBm into 50Ω load

Load impedance presented at RF OUT pinVRAMP=0.2V to VRAMP MAX, PIN=+5dBm

SpecificationMin.Typ.Max.

UnitCondition

Temp=25°C, VBATT=3.5V,

VRAMP =VRAMP MAX, VREG=2.8V, Freq=1850MHz to 1910MHz,

25% Duty Cycle, pulse width=11µs

+31.8+29.8

Total EfficiencyInput Power RangeOutput Noise PowerForward Isolation 1Forward Isolation 2Second HarmonicThird HarmonicAll Other

Non-Harmonic SpuriousInput ImpedanceInput VSWR

Output Load VSWR StabilityOutput Load VSWR RuggednessOutput Load Impedance

420

Temp=25°C, VBATT=3.5V,

VRAMP=VRAMP MAX, 1850MHz to 1910MHzTemp=+85°C, VBATT=3.1V,VRAMP=VRAMP MAX

At POUT MAX, VBATT=3.5V

Full output power guaranteed at minimum drive level

RBW=100kHz, 1930MHz to 1990MHz, POUT > 0dBm, VBATT=3.5V

TX_ENABLE=Low, PIN=+5dBm

TXEnable=High, VRAMP=0.2V, PIN=+5dBmVRAMP=0.2V to VRAMP MAX VRAMP=0.2V to VRAMP MAX VRAMP=0.2V to VRAMP MAX

50-8:110:1

5050

ΩdB

Power Control VRAMP

Power Control Range

Note: VRAMP MAX=3/8*VBATT+0.18<1.5VRev A1 0507192-495

RF9340

Pin123456710

FunctionDescriptionInterface SchematicDCS/PCS INRF input to the DCS/PCS band. This is a 50Ω input.

Allows external control to select the GSM or DCS/PCS bands with a BAND

logic high or low. A logic low enables the GSM bands, whereas a logic

SELECThigh enables the DCS/PCS bands.TX ENABLEVBATTVREGVRAMPGSM900 INVCC2GSM900OUTVCC OUT

This signal enables the PA module for operation with a logic high. Once TX Enable is asserted the RF output level will increase to -20dBm.Power supply for the module. This should be connected to the battery.Regulated voltage input for power control function. (2.8V nom)Ramping signal from DAC. A simple RC filter may need to be con-nected between the DAC output and the VRAMP input depending on the baseband selected.

RF input to the GSM bands. This is a 50Ω input.

Controlled voltage input to driver stage for GSM bands. This voltage is part of the power control function for the module. This node must be connected to VCC out.

RF output for the GSM bands. This is a 50Ω output. The output load line matching is contained internal to the package.

Controlled voltage output to feed VCC2. This voltage is part of the power control function for the module. It cannot be connected to anything other than VCC2, nor can any component be placed on this node (i.e., decoupling capacitor).

RF output for the DCS/PCS bands. This is a 50Ω output. The output load line matching is contained internal to the package.

Controlled voltage input to DCS/PCS driver stage. This voltage is part of the power control function for the module. This node must be con-nected to VCC out.

1112PkgBase

DCS/PCS OUT VCC2GND

2-496Rev A1 050719

RF9340

Pin Out

PIN #12CCVDCS/PCS INDCS/PCS OUTBAND SELECTTX ENVBATTVCC OUT10.0000VREGVRAMPGSM900 INGSM900 OUTC2CV10.0000Rev A1 0507192-497

RF9340

Theory of Operation

Overview

The RF9340 is a triple-band EGSM900, DCS1800, and PCS1900 power amplifier module that incorporates an indirectclosed loop method of power control. This simplifies the phone design by eliminating the need for the complicated controlloop design. The indirect closed loop appears as an open loop to the user and can be driven directly from the DAC outputin the baseband circuit.

Theory of Operation

The indirect closed loop is essentially a closed loop method of power control that is invisible to the user. Most power con-trol systems in GSM sense either forward power or collector/drain current. The RF9340 does not use a power detector. Ahigh-speed control loop is incorporated to regulate the collector voltage of the amplifier while the stage are held at a con-stant bias. The VRAMP signal is multiplied by a factor of 2.65 and the collector voltage for the second and third stages areregulated to the multiplied VRAMP voltage. The basic circuit is shown in the following diagram.

VBATTTX ENABLEVRAMPH(s)RF INTX ENABLERF OUT

By regulating the power, the stages are held in saturation across all power levels. As the required output power isdecreased from full power down to 0dBm, the collector voltage is also decreased. This regulation of output power isdemonstrated in Equation 1 where the relationship between collector voltage and output power is shown. Although loadimpedance affects output power, supply fluctuations are the dominate mode of power variations. With the RF9340 regu-lating collector voltage, the dominant mode of power fluctuations is eliminated.

PdBm

(2⋅VCC–VSAT)

-----=10⋅log--------------------------------------–3

8⋅RLOAD⋅10

2

(Eq. 1)

There are several key factors to consider in the implementation of a transmitter solution for a mobile phone. Some ofthem are:•••••••••••

Effective efficiency (ηeff)

Current draw and system efficiencyPower variation due to Supply VoltagePower variation due to frequencyPower variation due to temperatureInput impedance variationNoise powerLoop stability

Loop bandwidth variations across power levelsBurst timing and transient spectrum trade offsHarmonics

2-498Rev A1 050719

RF9340

Talk time and power management are key concerns in transmitter design since the power amplifier has the highest cur-rent draw in a mobile terminal. Considering only the power amplifier’s efficiency does not provide a true picture for thetotal system efficiency. It is important to consider effective efficiency which is represented by ηEFF. (ηEFF considers theloss between the PA and antenna and is a more accurate measurement to determine how much current will be drawn inthe application). ηEFF is defined by the following relationship (Equation 2):

m

∑PN–PIN

1----=----------------------------⋅100ηEFF=n

PDC

(Eq. 2)

Where PN is the sum of all positive and negative RF power, PIN the input power and PDC is the delivered DC power. In dBthe formula becomes (Equation 3):

10–10

ηEFF=------------------------------------------------VBAT⋅IBAT⋅10

PPA+PLOSS-----------------------------10P----IN---10

(Eq. 3)

Where PPA is the output power from the PA, PLOSS the insertion loss, PIN the input power to the PA and PDC the deliv-ered DC power.

The RF9340 improves the effective efficiency by minimizing the PLOSS term in the equation. A directional coupler may

introduce 0.4dB to 0.5dB loss to the transit path. To demonstrate the improvement in effective efficiency consider the fol-lowing example:

Conventional PA Solution at F=1785MHz:

PPA = +33.5 dBm PIN = +3 dBmPLOSS = -0.4 dB VBAT = 3.5 V IBAT = 1.16 A

RF9340 Solution:

ηEFF = 50.3%

PPA = +33.5 dBm PIN = +3 dBmPLOSS = 0 dB VBAT = 3.5 V IBAT = 1.16 A

hEFF = 55.16%

The RF9340 solution improves effective efficiency by 5%.

Output power does not vary due to supply voltage under normal operating conditions if VRAMP is sufficiently lower thanVBATT. By regulating the collector voltage to the PA the voltage sensitivity is essentially eliminated. This covers mostcases where the PA will be operated. However, as the battery discharges and approaches its lower power range themaximum output power from the PA will also drop slightly. In this case it is important to also decrease VRAMP to preventthe power control from inducing switching transients. These transients occur as a result of the control loop slowing downand not regulating power in accordance with VRAMP.

Rev A1 0507192-499

RF9340

The switching transients due to low battery conditions are regulated by incorporating the following relationship limitingthe maximum VRAMP voltage (Equation 4). Although no compensation is required for typical battery conditions, the bat-tery compensation required for extreme conditions is covered by the relationship in Equation 4. This should be added tothe terminal software.

3

VRAMP≤--⋅VCC+0.18

8

(Eq. 4)

Due to reactive output matches, there are output power variations across frequency. There are a number of componentsthat can make the effects greater or less. Power variation straight out of the RF9340 is shown in the tables below.The components following the power amplifier often have insertion loss variation with respect to frequency. Usually, thereis some length of microstrip that follows the power amplifier. There is also a frequency response found in directional cou-plers due to variation in the coupling factor over frequency, as well as the sensitivity of the detector diode. Since theRF9340 does not use a directional coupler with a diode detector, these variations do not occur.

Input impedance variation is found in most GSM power amplifiers. This is due to a device phenomena where CBE andCCB (CGS and CSG for a FET) vary over the bias voltage. The same principle used to make varactors is present in thepower amplifiers. The junction capacitance is a function of the bias across the junction. This produces input impedancevariations as the Vapc voltage is swept. Although this could present a problem with frequency pulling the transmit VCOoff frequency, most synthesizer designers use very wide loop bandwidths to quickly compensate for frequency variationsdue to the load variations presented to the VCO.

The RF9340 presents a very constant load to the VCO. This is because all stages of the RF9340 are run at constantbias. As a result, there is constant reactance at the base emitter and base collector junction of the input stage to thepower amplifier.

Noise power in PA's where output power is controlled by changing the bias voltage is often a problem when backing off ofoutput power. The reason is that the gain is changed in all stages and according to the noise formula (Equation 5),

F2–1F3–1

FTOT=F1+---------------+-------------------G1G1⋅G2

(Eq. 5)

the noise figure depends on noise factor and gain in all stages. Because the bias point of the RF9340 is kept constant

the gain in the first stage is always high and the overall noise power is not increased when decreasing output power.Power control loop stability often presents many challenges to transmitter design. Designing a proper power control loopinvolves trade-offs affecting stability, transient spectrum and burst timing.

In conventional architectures the PA gain (dB/ V) varies across different power levels, and as a result the loop bandwidthalso varies. With some power amplifiers it is possible for the PA gain (control slope) to change from 100dB/V to as highas 1000dB/V. The challenge in this scenario is keeping the loop bandwidth wide enough to meet the burst mask at lowslope regions which often causes instability at high slope regions.

The RF9340 loop bandwidth is determined by internal bandwidth and the RF output load and does not change withrespect to power levels. This makes it easier to maintain loop stability with a high bandwidth loop since the bias voltageand collector voltage do not vary.

An often overlooked problem in PA control loops is that a delay not only decreases loop stability it also affects the bursttiming when, for instance the input power from the VCO decreases (or increases) with respect to temperature or supplyvoltage. The burst timing then appears to shift to the right especially at low power levels. The RF9340 is insensitive to achange in input power and the burst timing is constant and requires no software compensation.

2-500Rev A1 050719

RF9340

Switching transients occur when the up and down ramp of the burst is not smooth enough or suddenly changes shape. Ifthe control slope of a PA has an inflection point within the output power range or if the slope is simply too steep it is diffi-cult to prevent switching transients. Controlling the output power by changing the collector voltage is as earlier describedbased on the physical relationship between voltage swing and output power. Furthermore all stages are kept constantlybiased so inflection points are nonexistent.

Harmonics are natural products of high efficiency power amplifier design. An ideal class “E” saturated power amplifierwill produce a perfect square wave. Looking at the Fourier transform of a square wave reveals high harmonic content.Although this is common to all power amplifiers, there are other factors that contribute to conducted harmonic content aswell. With most power control methods a peak power diode detector is used to rectify and sense forward power. Throughthe rectification process there is additional squaring of the waveform resulting in higher harmonics. The RF9340 addressthis by eliminating the need for the detector diode. Therefore the harmonics coming out of the PA should represent themaximum power of the harmonics throughout the transmit chain. This is based upon proper harmonic termination of thetransmit port. The receive port termination on the T/R switch as well as the harmonic impedance from the switch itselfwill have an impact on harmonics. Should a problem arise, these terminations should be explored.

The RF9340 incorporates many circuits that had previously been required external to the power amplifier. The shadedarea of the diagram below illustrates those components and the following table itemizes a comparison between theRF9340 Bill of Materials and a conventional solution:

ComponentPower Control ASICDirectional CouplerBufferAttenuator

Various PassivesMounting Yield (other than PA)Total

ConventionalSolution$0.80$0.20$0.05$0.05$0.05$0.12

$1.27

RF9340N/AN/AN/AN/AN/AN/A$0.00

1234567141312111098From DAC*Shaded area eliminated with Indirect Closed Loop using RF9340

Rev A1 0507192-501

RF9340

Application Schematic

1250 ΩµstripDCS/PCS INBAND SELECTTX ENABLE

VBATTVREG

15 kΩ**VRAMP

50 ΩµstripGSM900 IN

7650 ΩµstripGSM900 OUT

12345101150 ΩµstripDCS/PCS OUT

** Used to filter noise and spurious from base band.Evaluation Board Schematic

P11GNDP2-1CON150 ΩµstripDCS/PCS IN

6.8 pF1BAND SELECTTX ENABLE

VBATT

22 µF*15 kΩ**234VREG

5650 Ωµstrip7GSM900 OUT

101250 Ωµstrip11DCS/PCS OUT

P21VCCCON1VRAMPGSM900 IN

1 nF*50 Ωµstrip*Not required in most applications.** Used to filter noise and spurious from base band.

Note 1: All the PA output measurements are referenced to the PA output pad (Pin 11 and 9).Note 2: The 50 Ω microstrip between the PA output pad and the SMA connector has an

approximate insertion loss of 0.1 dB for EGSM900 and 0.2 dB for DCS1800/PCS1900 bands.

2-502Rev A1 050719

RF9340

Evaluation Board LayoutBoard Size 2.0” x 2.0”

Board Thickness 0.042”±10%, Board Material FR-4, Multi-Layer

Rev A1 0507192-503

RF9340

PCB Design Requirements

PCB Surface Finish

The PCB surface finish used for RFMD’s qualification process is electroless nickel, immersion gold. Typical thickness is3µinch to 8µinch gold over 180µinch nickel.

PCB Land Pattern Recommendation

PCB land patterns are based on IPC-SM-782 standards when possible. The pad pattern shown has been developed andtested for optimized assembly at RFMD; however, it may require some modifications to address company specificassembly processes. The PCB land pattern has been developed to accommodate lead and package tolerances.PCB Metal Land and Solder Mask Pattern

A = 0.80 (mm) Sq. Typ.

8.39 (mm) Typ.

7.00 (mm)5.60 (mm)4.20 (mm) Typ.

2.81 (mm)1.40 (mm)

0.00

Pin 1

AAAAAAAA

AA

A

A

A = 0.80 (mm) Sq. Typ.B = 2.17 x 6.40 (mm)

8.39 (mm) Typ.

7.49 (mm) Typ.6.60 (mm)6.00 (mm)5.20 (mm)5.11 (mm)3.30 (mm)3.21 (mm)2.41 (mm)1.78 (mm)0.98 (mm)

0. (mm) Typ.

7.00 (mm) Typ.5.60 (mm) Typ.4.20 (mm) Typ.2.81 (mm) Typ.1.40 (mm) Typ.

0.00

Pin 1

AAAAAAAAAAAAAA

A

ABA

A

AAAAAAA

AAAAAAA

AAAAAAA

4.20 (mm)

1.40 (mm) Typ.2.30 (mm) Typ.7.51 (mm) Typ.8.39 (mm) Typ.1.40 (mm) Typ.2.79 (mm) Typ.3.48 (mm)4.19 (mm) Typ.5.60 (mm) Typ.Metal Land PatternSolder Mask Pattern

Figure 1. PCB Metal Land and Solder Mask Pattern (Top View)

2-504

7.00 (mm) Typ.8.39 (mm) Typ.0.000.00Rev A1 050719

RF9340

Thermal Pad and Via Design

The PCB land pattern has been designed with a thermal pad that matches the exposed die paddle size on the bottom ofthe device.

Thermal vias are required in the PCB layout to effectively conduct heat away from the package. The via pattern shownhas been designed to address thermal, power dissipation and electrical requirements of the device as well as accommo-dating routing strategies.

The via pattern used for the RFMD qualification is based on thru-hole vias with 0.203mm to 0.330mm finished hole sizewith 0.025mm plating on via walls. If micro vias are used in a design, it is suggested that the quantity of vias beincreased by a 4:1 ratio to achieve similar results.

1.40 (mm) GridFigure 2. Thermal Pad and Via Design (RFMD qualification)

Rev A1 0507192-505

RF9340

2-506Rev A1 050719