BurrĆBrown Productsfrom Texas Instruments
ADS8405
SLAS427–DECEMBER2004
16-BIT,1.25-MSPS,UNIPOLARPSEUDO-DIFFERENTIALINPUT,MICROPOWERSAMPLINGANALOG-TO-DIGITALCONVERTERWITHPARALLELINTERFACE
FEATURES
••••••••••••
UnipolarPseudo-DifferentialInput,0VtoVref16-BitNMCat1.25MSPS
±2LSBINLMax,-1/+1.5LSBDNL
86dBSNR,-90dBTHDat100kHzInputZeroLatency
Internal4.096-VReferenceHigh-SpeedParallelInterfaceSingle5-VAnalogSupply
WideI/OSupply:2.7Vto5.25V
LowPower:155mWat1.25MHzTypPinCompatibleWithADS8411/840148-PinTQFPPackage
APPLICATIONS
••••••
DWDM
Instrumentation
High-Speed,High-Resolution,ZeroLatencyDataAcquisitionSystemsTransducerInterfaceMedicalInstrumentsCommunications
DESCRIPTION
TheADS8405isa16-bit,1.25-MHzA/Dconverterwithaninternal4.096-Vreference.Thedevicein-cludesa16-bitcapacitor-basedSARA/Dconverterwithinherentsampleandhold.TheADS8405offersafull16-bitinterfaceandan8-bitoptionwheredataisreadusingtwo8-bitreadcyclesifnecessary.TheADS8405hasaunipolarpseudo-differentialin-put.Itisavailableina48-leadTQFPpackageandischaracterizedovertheindustrial-40°Cto85°Ctem-peraturerange.
HighSpeedSARConverterFamily
Type/Speed
18-BitPseudo-Diff
18-BitPseudo-Bipolar,FullyDiff16-BitPseudo-Diff
16-BitPseudo-Bipolar,FullyDiff14-BitPseudo-Diff12-BitPseudo-Diff
ADS7886
500kHzADS8383
~600kHzADS8381ADS8380(S)ADS8382(S)
ADS8371
ADS8401/05ADS8402/06ADS7890(S)
ADS8411ADS8412
ADS7891
ADS7881
750kHz
1MHz
1.25MHz
2MHz
3MHz
4MHz
SAR+IN−INREFIN4.096-VInternalReference+_CDACComparatorOutputLatchesand3-StateDriversBYTE16-/8-BitParallel DATAOutput BusREFOUT
ClockConversionandControl LogicRESETCONVSTBUSYCSRDPleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
PRODUCTIONDATAinformationiscurrentasofpublicationdate.ProductsconformtospecificationsperthetermsoftheTexasInstrumentsstandardwarranty.Productionprocessingdoesnotnecessarilyincludetestingofallparameters.
Copyright©2004,TexasInstrumentsIncorporated
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ADS8405
SLAS427–DECEMBER2004
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ORDERINGINFORMATION(1)
MODEL
MAXIMUMINTEGRALLINEARITY(LSB)
MAXIMUMDIFFERENTIALLINEARITY(LSB)
NOMISSINGCODESRESOLUTION
(BIT)
PACKAGETYPE
PACKAGEDESIGNATOR
TEMPERATURE
RANGE
ORDERINGINFORMATION
TRANSPORTMEDIAQUANTITYTapeandreel
250Tapeandreel
1000Tapeandreel
250Tapeandreel
1000
ADS8405IPFBT
ADS8405I
–4to+4
–2to+2
15
48PinTQFP
PFB
–40°Cto85°C
ADS8405IPFBRADS8405IBPFBT
ADS8405IB
–2to+2
–1to+1.5
16
48PinTQFP
PFB
–40°Cto85°C
ADS8405IBPFBR
(1)Forthemostcurrentspecificationsandpackageinformation,refertoourwebsiteatwww.ti.com.
ABSOLUTEMAXIMUMRATINGS
overoperatingfree-airtemperaturerangeunlessotherwisenoted(1)
UNIT
+INtoAGND–INtoAGND
Voltage
+VAtoAGND+VBDtoBDGND+VAto+VBD
DigitalinputvoltagetoBDGNDDigitaloutputvoltagetoBDGND
TATstg
Operatingfree-airtemperaturerangeStoragetemperaturerangeJunctiontemperature(TJmax)TQFPpackage
PowerdissipationθJAthermalimpedance
Vaporphase(60sec)Infrared(15sec)
–0.4Vto+VA+0.1V
–0.4Vto0.5V–0.3Vto7V–0.3Vto7V–0.3Vto2.55V–0.3Vto+VBD+0.3V–0.3Vto+VBD+0.3V
–40°Cto85°C–65°Cto150°C
150°C(TJMax–TA)/θJA
86°C/W215°C220°C
Leadtemperature,soldering
(1)
Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.Thesearestressratingsonly,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperatingconditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability.
2
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SLAS427–DECEMBER2004
SPECIFICATIONS
TA=–40°Cto85°C,+VA=5V,+VBD=3Vor5V,Vref=4.096V,fSAMPLE=1.25MHz(unlessotherwisenoted)
PARAMETER
ANALOGINPUT
Full-scaleinputvoltageAbsoluteinputvoltageInputcapacitanceInputleakagecurrent
SYSTEMPERFORMANCE
ResolutionNomissingcodes
INLDNLEOEG
Integrallinearity
(2)(3)
(1)
TESTCONDITIONS
+IN–(–IN)+IN–IN
MIN0–0.2–0.2
TYPMAXVref
Vref+0.2
0.2
UNITVVpFnABitsBits
250.516
ADS8405IADS8405IBADS8405IADS8405IBADS8405IADS8405IBADS8405IADS8405IBADS8405IADS8405IB
AtFFFFhoutputcode,+VA=4.75Vto5.25V,Vref=4.096V(4)
500150
1.25
225100100
VIN=4Vp-pat100kHzVIN=4Vp-pat500kHzVIN=4Vp-pat100kHzVIN=4Vp-pat100kHzVIN=4Vp-pat100kHzVIN=4Vp-pat500kHz
–90–88.5868590885
2.5
4.096500
4.2
1516–4–2–2–1–3–1.5–0.15–0.098
602±2±1±1±0.75±1±0.5
4221.531.50.150.98
LSBLSBmVmV%FSµVRMSLSB
DifferentiallinearityOffseterror(4)Gainerror(4)(5)Noise
DCPowersupplyrejectionratio
SAMPLINGDYNAMICS
ConversiontimeAcquisitiontimeThroughputrateAperturedelayAperturejitterStepresponseOvervoltagerecovery
DYNAMICCHARACTERISTICSTHDSNRSINADSFDR
Totalharmonicdistortion(6)Signal-to-noiseratioSignal-to-noise+distortionSpuriousfreedynamicrange-3dBSmallsignalbandwidth
EXTERNALVOLTAGEREFERENCEINPUT
ReferencevoltageatREFIN,VrefReferenceresistance
(7)
650nsnsMHznspsnsnsdBdBdBdBdBdBMHzVkΩ
(1)(2)(3)(4)(5)(6)(7)Idealinputspan,doesnotincludegainoroffseterror.LSBmeansleastsignificantbitThisisendpointINL,notbestfit.
Measuredrelativetoanidealfull-scaleinput(+IN–(–IN))of4.096V.
Thisspecificationdoesnotincludetheinternalreferencevoltageerroranddrift.Calculatedonthefirstnineharmonicsoftheinputfrequency.Canvary±20%
3
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SPECIFICATIONS(continued)
TA=–40°Cto85°C,+VA=5V,+VBD=3Vor5V,Vref=4.096V,fSAMPLE=1.25MHz(unlessotherwisenoted)
PARAMETER
INTERNALREFERENCEOUTPUT
Internalreferencestart-uptimeVrefrangeSourcecurrentLineregulationDrift
DIGITALINPUT/OUTPUT
Logicfamily-CMOS
VIHVILVOHVOL
High-levelinputvoltageLow-levelinputvoltageHigh-leveloutputvoltageLow-leveloutputvoltageDataformat-straightbinary
POWERSUPPLYREQUIREMENTS
Powersupplyvoltage+VASupplycurrentPowerdissipation(8)
TEMPERATURERANGE
Operatingfree-air
(8)
–40
85
°C
(8)
TESTCONDITIONS
From95%(+VA),with1-µFstoragecapacitorIOUT=0Staticload
+VA=4.75Vto5.25VIOUT=0
MINTYPMAXUNIT
120
4.065
4.0960.636
4.1310
msVµAmVPPM/C
IIH=5µAIIL=5µAIOH=2TTLloadsIOL=2TTLloads
+VBD–1
–0.3
+VBD–0.6
0
+VBD+0.3
0.8+VBD0.4
V
+VBD+VA
fs=1.25MHzfs=1.25MHz
2.74.75
3531155
5.255.2534170
VVmAmW
ThisincludesonlyVA+current.+VBDcurrentistypically1mAwith5-pFloadcapacitanceonoutputpins.
4
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TIMINGCHARACTERISTICS
Allspecificationstypicalat–40°Cto85°C,+VA=+VBD=5V
PARAMETER
tCONVtACQtpd1tpd2tw1tsu1tw2tw3tw4th1td1tsu2tw5tentd2td3tw6tw7th2tsu3th3tdistd5tsu4td6td7tsu(AB)
ConversiontimeAcquisitiontime
CONVSTlowtoBUSYhigh
Propagationdelaytime,endofconversiontoBUSYlowPulseduration,CONVSTlowSetuptime,CSlowtoCONVSTlowPulseduration,CONVSThighCONVSTfallingedgejitterPulseduration,BUSYsignallowPulseduration,BUSYsignalhigh
Holdtime,firstdatabusdatatransition(RDlow,orCSlowforreadcycle,orBYTEinputchanges)afterCONVSTlow
Delaytime,CSlowtoRDlow(orBUSYlowtoRDlowwhenCS=0)Setuptime,RDhightoCShighPulseduration,RDlow
Enabletime,RDlow(orCSlowforreadcycle)todatavalidDelaytime,dataholdfromRDhigh
Delaytime,BYTErisingedgeorfallingedgetodatavalidPulseduration,RDhighPulseduration,CShigh
Holdtime,lastRD(orCSforreadcycle)risingedgetoCONVSTfallingedge
Setuptime,BYTEtransitiontoRDfallingedgeHoldtime,BYTEtransitiontoRDfallingedge
Disabletime,RDhigh(CShighforreadcycle)to3-stateddatabusDelaytime,endofconversiontoMSBdatavalid
Bytetransitionsetuptime,fromBYTEtransitiontonextBYTEtransition
Delaytime,CSrisingedgetoBUSYfallingedgeDelaytime,BUSYfallingedgetoCSrisingedge
Setuptime,fromthefallingedgeofCONVST(usedtostartthevalidconversion)tothenextfallingedgeofCONVST(whenCS=0andCONVSTusedtoabort)ortothenextfallingedgeofCS(whenCSisusedtoabort)
Setuptime,fallingedgeofCONVSTtoreadvaliddata(MSB)fromcurrentconversion
Holdtime,data(MSB)frompreviousconversionholdvalidfromfallingedgeofCONVST50505060
500
0220205000
201020
400050
20
Min(tACQ)
610
20020
10
(1)(2)(3)
MIN500150
TYPMAX650
UNITnsnsnsnsnsnsnspsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns
405
tsu5th4(1)(2)(3)
MAX(tCONV)+MAX(td5)
MIN(tCONV)
nsns
Allinputsignalsarespecifiedwithtr=tf=5ns(10%to90%of+VBD)andtimedfromavoltagelevelof(VIL+VIH)/2.Seetimingdiagrams.
Alltimingsaremeasuredwith20-pFequivalentloadsonalldatabitsandBUSYpins.
5
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TIMINGCHARACTERISTICS
Allspecificationstypicalat–40°Cto85°C,+VA=5V,+VBD=3V(1)(2)(3)
PARAMETER
tCONVtACQtpd1tpd2tw1tsu1tw2tw3tw4th1td1tsu2tw5tentd2td3tw6tw7th2tsu3th3tdistd5tsu4td6td7tsu(AB)
ConversiontimeAcquisitiontime
CONVSTlowtoBUSYhigh
Propagationdelaytime,endofconversiontoBUSYlowPulseduration,CONVSTlowSetuptime,CSlowtoCONVSTlowPulseduration,CONVSThighCONVSTfallingedgejitterPulseduration,BUSYsignallowPulseduration,BUSYsignalhigh
Holdtime,firstdatabustransition(RDlow,orCSlowforreadcycle,orBYTEinputchanges)afterCONVSTlow
Delaytime,CSlowtoRDlow(orBUSYlowtoRDlowwhenCS=0)Setuptime,RDhightoCShighPulseduration,RDlow
Enabletime,RDlow(orCSlowforreadcycle)todatavalidDelaytime,dataholdfromRDhigh
Delaytime,BYTErisingedgeorfallingedgetodatavalidPulseduration,RDhighPulseduration,CShigh
Holdtime,lastRD(orCSforreadcycle)risingedgetoCONVSTfallingedge
Setuptime,BYTEtransitiontoRDfallingedgeHoldtime,BYTEtransitiontoRDfallingedge
Disabletime,RDhigh(CShighforreadcycle)to3-stateddatabusDelaytime,endofconversiontoMSBdatavalid
Bytetransitionsetuptime,fromBYTEtransitiontonextBYTEtransition
Delaytime,CSrisingedgetoBUSYfallingedgeDelaytime,BUSYfallingedgetoCSrisingedge
Setuptime,fromthefallingedgeofCONVST(usedtostartthevalidconversion)tothenextfallingedgeofCONVST(whenCS=0andCONVSTusedtoabort)ortothenextfallingedgeofCS(whenCSisusedtoabort)
Setuptime,fallingedgeofCONVSTtoreadvaliddata(MSB)fromcurrentconversion
Holdtime,data(MSB)frompreviousconversionholdvalidfromfallingedgeofCONVST50505070
500
0220205000
302030
400050
30
Min(tACQ)
610
20020
10
MIN500150
5010TYP
MAX650
UNITnsnsnsnsnsnsnspsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns
tsu5th4(1)(2)(3)
MAX(tCONV)+MAX(td5)
MIN(tCONV)
nsns
Allinputsignalsarespecifiedwithtr=tf=5ns(10%to90%of+VBD)andtimedfromavoltagelevelof(VIL+VIH)/2.Seetimingdiagrams.
Alltimingsaremeasuredwith10-pFequivalentloadsonalldatabitsandBUSYpins.
6
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PINASSIGNMENTS
PFB PACKAGE(TOP VIEW)
+VBDRESETBYTECONVSTRDCS+VAAGNDAGND+VAREFMREFMBUSYBDGND+VBDDB0DB1DB2DB3DB4DB5DB6DB7BDGND363534333231302928272625373839404142434445464748123456782423222120191817161514139101112+VBDDB8DB9DB10DB11DB12DB13DB14DB15AGNDAGND+VA
REFINREFOUTNC+VAAGND+IN-INAGND+VA+VANC - No connection
AGNDAGND7
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TerminalFunctions
NAMEAGNDBDGNDBUSYBYTECONVSTCSDataBusDB15DB14DB13DB12DB11DB10DB9DB8DB7DB6DB5DB4DB3DB2DB1DB0–IN+INNCREFINREFMREFOUTRESETRD+VA+VBD
16171819202122232627282930313233763147,48238414,9,10,13,43,
4624,34,37
OOOOOOOOOOOOOOOOII–IIOII––
NO.5,8,11,12,14,15,44,45
25,3536394042
I/O––OIII
Analogground
DigitalgroundforbusinterfacedigitalsupplyStatusoutput.Highwhenaconversionisinprogress.
Byteselectinput.Usedfor8-bitbusreading.0:Nofoldback1:LowbyteD[7:0]ofthe16mostsignificantbitsisfoldedbacktohighbyteofthe16mostsignificantpinsDB[15:8].Convertstart.Thefallingedgeofthisinputendstheacquisitionperiodandstartstheholdperiod.
Chipselect.Thefallingedgeofthisinputstartstheacquisitionperiod.
8-BitBus
BYTE=0D15(MSB)
D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0(LSB)
InvertinginputchannelNoninvertinginputchannelNoconnectionReferenceinputReferenceground
Referenceoutput.Add1-µFcapacitorbetweentheREFOUTpinandREFMpinwhentheinternalreferenceisused.
Currentconversionisabortedandoutputlatchesarecleared(settozeros)whenthispinisassertedlow.RESETworksindependantlyofCS.Synchronizationpulsefortheparalleloutput.WhenCSislow,thisservesastheoutputenableandputsthepreviousconversionresultonthebus.Analogpowersupplies,5-VdcDigitalpowersupplyforbus
BYTE=1
D7D6D5D4D3D2D1D0(LSB)AllonesAllonesAllonesAllonesAllonesAllonesAllonesAllones
16-BitBusBYTE=0D15(MSB)
D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0(LSB)
DESCRIPTION
8
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TIMINGDIAGRAMS
tw1CONVST(used in normalconversion)CONVST(used in ABORT)tsu(AB)tpd1BUSYtsu1CStd6CONVERT†tCONVSAMPLING†(When CS Toggle)tACQBYTEtsu4th1td1RDData tobe read†InvalidPrevious Conversionth4DB[15:8]tsu5Hi−ZD [15:8]DB[7:0]†Signal internal to device
tw2tcycletsu(AB)tpd2tw3tw7tpd1tw4td7tCONVtsu2th2InvalidCurrent ConversiontenD [7:0]Hi−ZD [7:0]tdisHi−ZHi−ZFigure1.TimingforConversionandAcquisitionCyclesWithCSandRDToggling
9
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TIMINGDIAGRAMS(continued)
tw1CONVST(used in normalconversion)CONVST(used in ABORT)tsu(AB)tpd1BUSYtsu1CStd6CONVERT†tCONVSAMPLING†(When CS Toggle)tACQBYTEth1RD = 0Data tobe read†tenth4DB[15:8]PreviousHi−ZD [15:8]Hi−ZPreviousD [7:0]tdisPrevious Conversiontsu5Hi−ZD [15:8]D [7:0]Hi−ZHi−ZtenInvalidCurrent Conversiontentsu4th2tdisInvalidtCONVtd7tw4tpd2tw3tw7tsu(AB)tcycletw2RepeatedD [15:8]RepeatedD [7:0]DB[7:0]Hi−ZD [7:0]†Signal internal to deviceFigure2.TimingforConversionandAcquisitionCyclesWithCSToggling,RDTiedtoBDGND
10
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TIMINGDIAGRAMS(continued)
tw1CONVST(used in normalconversion)CONVST(used in ABORT)tsu(AB)tpd1BUSYtw4tpd2tw3tpd1tsu(AB)tcycletw2CS = 0CONVERT†tCONVSAMPLING†(When CS = 0)BYTEth1tsu4th2RDtenData tobe read†InvalidPrevious Conversionth4DB[15:8]tsu5Hi−ZD [15:8]D [7:0]Hi−ZCurrent ConversiontdisInvalidt(ACQ)tCONVDB[7:0]†Signal internal to device
Hi−ZD [7:0]Hi−ZFigure3.TimingforConversionandAcquisitionCyclesWithCSTiedtoBDGND,RDToggling
11
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TIMINGDIAGRAMS(continued)
tw1CONVST(used in normalconversion)CONVST(used in ABORT)tsu(AB)tpd1BUSYtw4tpd2tw3tpd1tsu(AB)tcycletw2tpd2CS = 0CONVERT†tCONVtACQSAMPLING†(When CS Toggle)th1BYTEth1tCONVRD = 0td3th4tsu5td5td3MSBInvalidMSBLSBLSBtd3th4td5tsu5InvalidDB[15:8]PreviousMSBPreviousPreviousLSBLSBInvalidMSBInvalidMSBDB[7:0]†Signal internal to device
Figure4.TimingforConversionandAcquisitionCyclesWithCSandRDTiedtoBDGND—AutoRead
CSRDtsu4BYTE
tentenDB[15:0]
Hi−ZValidtdisHi−ZValidValidtd3tdisHi−ZFigure5.DetailedTimingforReadCycles
12
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TYPICALCHARACTERISTICS
At–40°Cto85°C,+VA=5V,+VBD=5V,REFIN=4.096V(internalreferenceused)andfsample=1.25MHz(unlessotherwisenoted)
HISTOGRAM(DCCodeSpread)HALFSCALE131071CONVERSIONS
80000
+VA = 5 V,TA = 25°C,Code = 652925000040000300002000010000
65289652950
SNR − Signal-to-Noise Ratio − dB7000060000
+VBD = 3.3 V,86.686.486.28685.885.685.485.2
65292−40−25−105
20
35
50
65
80
TA − Free-Air Temperature −5Cfi = 50 kHz,Full Scale Input,+VA = 5 V,+VBD = 3 V,Int Ref = 4.096 V86.8
SIGNAL-TO-NOISERATIO
vs
FREE-AIRTEMPERATURE
Figure6.
SIGNAL-TO-NOISEANDDISTORTION
vs
FREE-AIRTEMPERATURE
SINAD − Signal-to-Noise and Distortion − dB83.683.483.28382.882.682.482.282
fi = 50 kHz,Full Scale Input,+VA = 5 V,+VBD = 3 V,Int Ref = 4.096 V80
ENOB − Effective Number of Bits − Bits13.613.5513.513.4513.413.3513.313.25
Figure7.
EFFECTIVENUMBEROFBITS
vs
FREE-AIRTEMPERATURE
fi = 50 kHz,Full Scale Input,+VA = 5 V,+VBD = 3 V,Int Ref = 4.096 V−40−25−105203550658081.8
−40−25−10520355065
TA − Free-Air Temperature − 5C
TA − Free-Air Temperature − 5C
Figure8.Figure9.
13
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TYPICALCHARACTERISTICS(continued)
SPURIOUSFREEDYNAMICRANGE
vs
FREE-AIRTEMPERATURE
SFDR − Spurious Free Dynamic Range − dB95THD − Total Harmonic Distortion − dBTOTALHARMONICDISTORTION
vs
FREE-AIRTEMPERATURE
−90
fi = 50 kHz,Full Scale Input,+VA = 5 V,+VBD = 3 V,Int Ref = 4.096 V94−91
93−92
92fi = 50 kHz,Full Scale Input,+VA = 5 V,+VBD = 3 V,Int Ref = 4.096 V20
35
50
65
80
−93
91−94
90−40−25−105
TA − Free-Air Temperature − 5C
−95
−40−25−10520355065
TA − Free-Air Temperature − 5C
80
Figure10.
SIGNAL-TO-NOISERATIO
vs
INPUTFREQUENCY
ENOB − Effective Number of Bits − Bits86.9SNR − Signal-to-Noise Ratio − dB86.886.786.686.586.486.386.286.1860
102030405060708090100
fi − Input Frequency − kHzfi = 50 kHz,Full Scale Input,+VA = 5 V,+VBD = 3 V,Int Ref = 4.096 V13.913.8513.813.7513.713.6513.613.5513.513.4513.40
Figure11.
EFFECTIVENUMBEROFBITS
vs
INPUTFREQUENCY
fi = 50 kHz,Full Scale Input,+VA = 5 V,+VBD = 3 V,Int Ref = 4.096 V10203040
5060
708090100
fi − Input Frequency − kHz
Figure12.
SIGNAL-TO-NOISEANDDISTORTION
vs
INPUTFREQUENCY
SINAD − Signal-to-Noise and Distortion − dBSFDR − Spurious Free Dynamic Range − dB85.58584.58483.58382.5
0102030405060708090100fi − Input Frequency − kHz
Figure13.
SPURIOUSFREEDYNAMICRANGE
vs
INPUTFREQUENCY
1011009998979695949392910
fi = 50 kHz,Full Scale Input,+VA = 5 V,+VBD = 3 V,Int Ref = 4.096 V102030405060708090100
fi − Input Frequency − kHz
fi = 50 kHz,Full Scale Input,+VA = 5 V,+VBD = 3 V,Int Ref = 4.096 VFigure14.Figure15.
14
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TYPICALCHARACTERISTICS(continued)
TOTALHARMONICDISTORTION
vs
INPUTFREQUENCY
−91THD − Total Harmonic Distortion − dB−92−93−94−95−96−97−98−99−100−101
0
102030405060708090100
fi − Input Frequency − kHzfi = 50 kHz,Full Scale Input,+VA = 5 V,+VBD = 3 V,Int Ref = 4.096 V2928.5ICC− Supply Current − mA2827.52726.52625.525250
+VA = 5 V,+VBD = 3.3 V,TA = 25°C,Int Ref = 4.096 VSUPPLYCURRENT
vs
SAMPLERATE
50075010001250
Sample Rate − KSPS
Figure16.GAINERROR
vs
SUPPLYVOLTAGE
0.150.1Gain Error − mV0.050−0.05−0.1−0.15
4.75+VBD = 3.3 V,TA = 25°C,Ext Ref = 4.096 VOffset Voltage − mV0.30.250.20.150.10.0504.75
Figure17.OFFSETERROR
vs
SUPPLYVOLTAGE
+VBD = 3.3 V,TA = 25°C,Ext Ref = 4.096 V5VCC − Supply Voltage − V
5.255
VCC − Supply Voltage − V
5.25
Figure18.
INTERNALVOLTAGEREFERENCE
vs
FREE-AIRTEMPERATURE
4.093Internal Reference Output Voltage − V4.0924.091
Gain Error − mV4.0904.0894.0884.0874.0864.0854.0844.0834.082
−40−25−1052035506580+VA = 5 V+VBD = 3.3 V0.50.40.30.20.10−0.1−0.2−0.3−0.4Figure19.
GAINERROR
vs
FREE-AIRTEMPERATURE
+VA = 5 V,+VBD = 3.3 V,Ext Ref = 4.096 VTA − Free-Air Temperature − 5C
−0.5−40−25−10520355065TA − Free-Air Temperature − 5C
80Figure20.Figure21.
15
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TYPICALCHARACTERISTICS(continued)
OFFSETERROR
vs
FREE-AIRTEMPERATURE
0.50.450.4Offset Voltage − mV0.350.30.250.20.150.10.050
−40−25−1052035506580+VA = 5 V,+VBD = 3.3 V,Ext Ref = 4.096 V29.229ICC− Supply Current − mA28.828.628.428.22827.8
+VA = 5 V,+VBD = 3.3 VSUPPLYCURRENT
vs
FREE-AIRTEMPERATURE
−40−25−1052035506580TA − Free-Air Temperature − 5CTA − Free-Air Temperature − 5C
Figure22.
DIFFERENTIALNONLINEARITY
vs
FREE-AIRTEMPERATURE
0.8DNL − Differential Nonlinearity − BitsMaxINL − Integral Nonlinearity − Bits0.60.40.20−0.2−0.4−0.6−0.8−40−25−105
20
35
50
65
80
Min+VA = 5 V,+VBD = 3.3 V,Ext Ref = 4.096 V10.51.5
Figure23.
INTEGRALNONLINEARITY
vs
FREE-AIRTEMPERATURE
Max0−0.5
+VA = 5 V,+VBD = 3.3 V,Ext Ref = 4.096 VMin−1
−1.5
−40−25−1052035506580TA − Free-Air Temperature − 5CTA − Free-Air Temperature − 5C
Figure24.
DIFFERENTIALNONLINEARITY
vs
REFERENCEVOLTAGE
2DNL − Differential Nonlinearity − BitsINL − Integral Nonlinearity − Bits1.510.50−0.5−1−1.5−22.533.5VREF − Reference Voltage − V
4Min+VA = 5 V,+VBD = 3.3 V,Ext Ref = VariedMax21.510.50−0.5−1−1.5−22.5
Figure25.
INTEGRALNONLINEARITY
vs
REFERENCEVOLTAGE
Max+VA = 5 V,+VBD = 3.3 V,Ext Ref = VariedMin33.5
VREF − Reference Voltage − V
4
Figure26.Figure27.
16
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ADS8405
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SLAS427–DECEMBER2004
TYPICALCHARACTERISTICS(continued)
DNL2.521.51DNL − LSBs0.50−0.5−1−1.5−2−2.501638432768Code
4915265536+VA = 5 V,+VBD = 5 V,TA = 25°C,Ext Ref = 4.096 VFigure28.INL2.521.51INL − LSBs0.50−0.5−1−1.5−2−2.501638432768Code
4915265536+VA = 5 V,+VBD = 5 V,TA = 25°C,Ext Ref = 4.096 VFigure29.FFT
0+VA = 5 V,+VBD = 3.3 V,REF +32768 Points,fi = 100 kHz,fs = 1.25 MHz,TA = 25°C,Int Ref = 4.096 V−50Amplitude −100−150−2000
200400
Frequency − kHz
600
Figure30.
17
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www.ti.com
APPLICATIONINFORMATION
MICROCONTROLLERINTERFACING
ADS8405to8-BitMicrocontrollerInterface
Figure31showsaparallelinterfacebetweentheADS8405andatypicalmicrocontrollerusingthe8-bitdatabus.TheBUSYsignalisusedasafalling-edgeinterrupttothemicrocontroller.
Analog 5 V
0.1 µFAGND10 µFExt Ref Input
1 µF0.1 µFAnalog Input
REFMAGND+IN−INMicroControllerGPIOGPIOP[7:0]RDGPIOINT+VAREFINDigital 3 VCSBYTEDB[15:8]RDCONVSTBUSYADS8405BDGNDBDGND+VBD0.1 µFFigure31.ADS8405ApplicationCircuitry(UsinganExternalReference)
Analog 5 V
0.1 µF10 µFAGND0.1 µF1 µFREFOUTREFM+VAREFINAGNDAGND
ADS8405Figure32.UsingtheInternalReference
PRINCIPLESOFOPERATION
TheADS8405isahigh-speedsuccessiveapproximationregister(SAR)analog-to-digitalconverter(ADC).Thearchitectureisbasedonchargeredistribution,whichinherentlyincludesasample/holdfunction.SeeFigure31fortheapplicationcircuitfortheADS8405.
Theconversionclockisgeneratedinternally.Theconversiontimeof650nsiscapableofsustaininga1.25-MHzthroughput.
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PRINCIPLESOFOPERATION(continued)
Theanaloginputisprovidedtotwoinputpins:+INand–IN.Whenaconversionisinitiated,thedifferentialinputonthesepinsissampledontheinternalcapacitorarray.Whileaconversionisinprogress,bothinputsaredisconnectedfromanyinternalfunction.
REFERENCE
TheADS8405canoperatewithanexternalreferencewitharangefrom2.5Vto4.2V.A4.096-Vinternalreferenceisincluded.Whenaninternalreferenceisused,pin2(REFOUT)shouldbeconnectedtopin1(REFIN)witha0.1-µFdecouplingcapacitoranda1-µFstoragecapacitorbetweenpin2(REFOUT)andpins47and48(REFM)(seeFigure32).Theinternalreferenceoftheconverterisdoublebuffered.Ifanexternalreferenceisused,thesecondbufferprovidesisolationbetweentheexternalreferenceandtheCDAC.ThisbufferisalsousedtorechargeallofthecapacitorsoftheCDACduringconversion.Pin2(REFOUT)canbeleftunconnected(floating)ifanexternalreferenceisused.
ANALOGINPUT
Whentheconverterentersholdmode,thevoltagedifferencebetweenthe+INand-INinputsiscapturedontheinternalcapacitorarray.Thevoltageonthe–INinputislimitedbetween–0.2Vand0.2V,allowingtheinputtorejectsmallsignalswhicharecommontoboththe+INand–INinputs.The+INinputhasarangeof–0.2VtoVref+0.2V.Theinputspan(+IN–(–IN))islimitedto0VtoVref.
Theinputcurrentontheanaloginputsdependsuponanumberoffactors:samplerate,inputvoltage,andsourceimpedance.Essentially,thecurrentintotheADS8405chargestheinternalcapacitorarrayduringthesampleperiod.Afterthiscapacitancehasbeenfullycharged,thereisnofurtherinputcurrent.Thesourceoftheanaloginputvoltagemustbeabletochargetheinputcapacitance(25pF)toan16-bitsettlinglevelwithintheacquisitiontime(150ns)ofthedevice.Whentheconvertergoesintoholdmode,theinputimpedanceisgreaterthan1GΩ.Caremustbetakenregardingtheabsoluteanaloginputvoltage.Tomaintainthelinearityoftheconverter,the+INand–INinputsandthespan(+IN–(–IN))shouldbewithinthelimitsspecified.Outsideoftheseranges,theconverter'slinearitymaynotmeetspecifications.Tominimizenoise,lowbandwidthinputsignalswithlow-passfiltersshouldbeused.
Careshouldbetakentoensurethattheoutputimpedanceofthesourcesdrivingthe+INand–INinputsarematched.Ifthisisnotobserved,thetwoinputscouldhavedifferentsettingtimes.Thismayresultinoffseterror,gainerror,andlinearityerrorwhichvarieswithtemperatureandinputvoltage.AtypicalinputcircuitusingTI'sTHS4031isshowninFigure33.300W15 V0.1 mF1 mF300W_THS4031G = +215 W+INADS84056800 pF0.1 mF−IN1 mFVIN+−15 VFigure33.UsingtheTHS4031withtheADS8405
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PRINCIPLESOFOPERATION(continued)DIGITALINTERFACE
TimingAndControl
Seethetimingdiagramsinthespecificationssectionfordetailedinformationontimingsignalsandtheirrequirements.
TheADS8405usesaninternaloscillatorgeneratedclockwhichcontrolstheconversionrateandinturnthethroughputoftheconverter.Noexternalclockinputisrequired.
ConversionsareinitiatedbybringingtheCONVSTpinlowforaminimumof20ns(afterthe20nsminimumrequirementhasbeenmet,theCONVSTpincanbebroughthigh)whileCSislow.TheADS8405switchesfromthesampletotheholdmodeonthefallingedgeoftheCONVSTcommand.Acleanandlowjitterfallingedgeofthissignalisimportanttotheperformanceoftheconverter.TheBUSYoutputisbroughthighafterCONVSTgoeslow.BUSYstayshighthroughouttheconversionprocessandreturnslowwhentheconversionhasended.SamplingstartsassoonastheconversionisoverwhenCSistiedloworstartswiththefallingedgeofCSwhenBUSYislow.
BothRDandCScanbehighduringandbeforeaconversionwithoneexception(CSmustbelowwhenCONVSTgoeslowtoinitiateaconversion).BoththeRDandCSpinsarebroughtlowinordertoenabletheparalleloutputbuswiththeconversion.ReadingData
TheADS8405outputsfullparalleldatainstraightbinaryformatasshowninTable1.TheparalleloutputisactivewhenCSandRDarebothlow.ThereisaminimalquietzonerequirementaroundthefallingedgeofCONVST.Thisis50nspriortothefallingedgeofCONVSTand40nsafterthefallingedge.Nodatareadshouldbeattemptedwithinthiszone.AnyothercombinationofCSandRDsetstheparalleloutputto3-state.BYTEisusedformultiwordreadoperations.BYTEisusedwheneverlowerbitsoftheconverterresultareoutputonthehigherbyteofthebus.RefertoTable1foridealoutputcodes.
Table1.IdealInputVoltagesandOutputCodes
DESCRIPTION
Fullscalerange
Leastsignificantbit(LSB)FullscaleMidscaleMidscale–1LSBZero
+Vref
(+Vref)/65536(+Vref)–1LSB(+Vref)/2(+Vref)/2–1LSB0V
ANALOGVALUE
DIGITALOUTPUTSTRAIGHTBINARYBINARYCODE1111111111111111100000000000000001111111111111110000000000000000
HEXCODEFFFF80007FFF0000
Theoutputdataisafull16-bitword(D15–D0)ontheDB15–DB0pins(MSB-LSB)ifBYTEislow.
Theresultmayalsobereadonan8-bitbusforconvenience.ThisisdonebyusingonlypinsDB15–DB8.Inthiscasetworeadsarenecessary:thefirstasbefore,leavingBYTElowandreadingthe8mostsignificantbitsonpinsDB15–DB8,thenbringingBYTEhigh.WhenBYTEishigh,thelowbits(D7–D0)appearonpinsDB15–D8.
ThesemultiwordreadoperationscanbedonewithmultipleactiveRD(toggling)orwithRDtiedlowforsimplicity.
ConversionDataReadout
BYTEHighLow
DATAREADOUT
DB15–DB8PinsD7–D0D15–D8
DB7–DB0PinsAllone'sD7-D0
20
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RESETRESETisanasynchronousactivelowinputsignal(thatworksindependentlyofCS).MinimumRESETlowtimeis25ns.Thecurrentconversionisabortednolaterthan50nsaftertheconverterisinresetmode.Inaddition,alloutputlatchesarecleared(settozero's)afterRESET.Theconvertergoesbacktonormaloperationmodenolaterthan20nsaftertheRESETinputisbroughthigh.
Theconverterstartsthefirstsamplingperiod20nsaftertherisingedgeofRESET.AnysamplingperiodexceptfortheoneimmediatelyafteraRESETisstartedwiththefallingedgeofthepreviousBUSYsignalorthefallingedgeofCS,whicheverislater.
AnotherwaytoresetthedeviceisthroughtheuseofthecombinationofCSandCONVST.ThisisusefulwhenthededicatedRESETpinistiedtothesystemresetbutthereisaneedtoabortonlytheconversioninaspecificconverter.SincetheBUSYsignalisheldhighduringtheconversion,eitheroneoftheseconditionstriggersaninternalself-clearresettotheconverterjustthesameasaresetviathededicatedRESETpin.TheresetdoesnothavetobeclearedasforthededicatedRESETpin.Aresetcanbestartedwitheitherofthetwofollowingsteps.
•IssueaCONVSTwhenCSislowandaconversionisinprogress.ThefallingedgeofCONVSTmustsatisfy
thetimingasspecifiedbythetimingparametertsu(AB)specifiedinthetimingcharacteristicstabletoensureareset.ThefallingedgeofCONVSTstartsareset.ThetimingisthesameasaresetusingthededicatedRESETpinexcepttheinstanceofthefallingedgeisreplacedbythefallingedgeofCONVST.•IssueaCSwhileaconversionisinprogress.ThefallingedgeofCSmustsatisfythetimingasspecifiedby
thetimingparametertsu(AB)specifiedinthetimingcharacteristicstabletoensureareset.ThefallingedgeofCScausesareset.ThetimingisthesameasaresetusingthededicatedRESETpinexcepttheinstanceofthefallingedgeisreplacedbythefallingedgeofCS.POWER-ONINITIALIZATION
RESETisnotrequiredafterpoweron.Aninternalpower-onresetcircuitgeneratesthereset.Toensurethatalloftheregistersarecleared,thethreeconversioncyclesmustbegiventotheconverterafterpoweron.
LAYOUT
Foroptimumperformance,careshouldbetakenwiththephysicallayoutoftheADS8405circuitry.
AstheADS8405offerssingle-supplyoperation,itisoftenusedincloseproximitywithdigitallogic,microcontrollers,microprocessors,anddigitalsignalprocessors.Themoredigitallogicpresentinthedesignandthehighertheswitchingspeed,themoredifficultitistoachievegoodperformancefromtheconverter.
ThebasicSARarchitectureissensitivetoglitchesorsuddenchangesonthepowersupply,reference,groundconnections,anddigitalinputsthatoccurjustpriortolatchingtheoutputoftheanalogcomparator.Thus,drivinganysingleconversionforann-bitSARconverter,thereareatleastnwindowsinwhichlargeexternaltransientvoltagescanaffecttheconversionresult.Suchglitchesmightoriginatefromswitchingpowersupplies,nearbydigitallogic,orhighpowerdevices.
Thedegreeoferrorinthedigitaloutputdependsonthereferencevoltage,layout,andtheexacttimingoftheexternalevent.
Onaverage,theADS8405drawsverylittlecurrentfromanexternalreference,asthereferencevoltageisinternallybuffered.Ifthereferencevoltageisexternalandoriginatesfromanopamp,makesurethatitcandrivethebypasscapacitororcapacitorswithoutoscillation.A0.1-µFbypasscapacitoranda1-µFstoragecapacitorarerecommendedfrompin1(REFIN)directlytopin48(REFM).REFMandAGNDshouldbeshortedonthesamegroundplaneunderthedevice.
TheAGNDandBDGNDpinsshouldbeconnectedtoacleangroundpoint.Inallcases,thisshouldbetheanalogground.Avoidconnectionswhichareclosetothegroundingpointofamicrocontrollerordigitalsignalprocessor.Ifrequired,runagroundtracedirectlyfromtheconvertertothepowersupplyentrypoint.Theideallayoutconsistsofananaloggroundplanededicatedtotheconverterandassociatedanalogcircuitry.
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www.ti.com
AswiththeAGNDconnections,+VAshouldbeconnectedtoa5-Vpowersupplyplaneortracethatisseparatefromtheconnectionfordigitallogicuntiltheyareconnectedatthepowerentrypoint.PowertotheADS8405shouldbecleanandwellbypassed.A0.1-µFceramicbypasscapacitorshouldbeplacedasclosetothedeviceaspossible.SeeTable2fortheplacementofthecapacitor.Inaddition,a1-µFto10-µFcapacitorisrecommended.Insomesituations,additionalbypassingmayberequired,suchasa100-µFelectrolyticcapacitororevenaPifiltermadeupofinductorsandcapacitors—alldesignedtoessentiallylow-passfilterthe5-Vsupply,removingthehighfrequencynoise.
Table2.PowerSupplyDecouplingCapacitorPlacement
POWERSUPPLYPLANESUPPLYPINS
PinpairsthatrequireshortestpathtodecouplingcapacitorsPinsthatrequirenodecoupling
CONVERTERANALOGSIDE(4,5),(8,9),(10,11),(13,15),(43,44),(45,46)12,14
CONVERTERDIGITALSIDE(24,25),(34,35)37
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PACKAGEOPTIONADDENDUM
www.ti.com
6-Dec-2006
PACKAGINGINFORMATION
OrderableDeviceADS8405IBPFBRADS8405IBPFBRG4ADS8405IBPFBTADS8405IBPFBTG4ADS8405IPFBRADS8405IPFBRG4ADS8405IPFBTADS8405IPFBTG4
(1)
Status(1)ACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVE
PackageTypeTQFPTQFPTQFPTQFPTQFPTQFPTQFPTQFP
PackageDrawingPFBPFBPFBPFBPFBPFBPFBPFB
PinsPackageEcoPlan(2)
Qty4848484848484848
1000Green(RoHS&
noSb/Br)1000Green(RoHS&
noSb/Br)250250
Green(RoHS&noSb/Br)Green(RoHS&noSb/Br)
Lead/BallFinishCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAU
MSLPeakTemp(3)Level-2-260C-1YEARLevel-2-260C-1YEARLevel-2-260C-1YEARLevel-2-260C-1YEARLevel-2-260C-1YEARLevel-2-260C-1YEARLevel-2-260C-1YEARLevel-2-260C-1YEAR
1000Green(RoHS&
noSb/Br)1000Green(RoHS&
noSb/Br)250250
Green(RoHS&noSb/Br)Green(RoHS&noSb/Br)
Themarketingstatusvaluesaredefinedasfollows:ACTIVE:Productdevicerecommendedfornewdesigns.
LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect.
NRND:Notrecommendedfornewdesigns.Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartinanewdesign.
PREVIEW:Devicehasbeenannouncedbutisnotinproduction.Samplesmayormaynotbeavailable.OBSOLETE:TIhasdiscontinuedtheproductionofthedevice.
(2)
EcoPlan-Theplannedeco-friendlyclassification:Pb-Free(RoHS),Pb-Free(RoHSExempt),orGreen(RoHS&noSb/Br)-pleasecheckhttp://www.ti.com/productcontentforthelatestavailabilityinformationandadditionalproductcontentdetails.TBD:ThePb-Free/Greenconversionplanhasnotbeendefined.
Pb-Free(RoHS):TI'sterms\"Lead-Free\"or\"Pb-Free\"meansemiconductorproductsthatarecompatiblewiththecurrentRoHSrequirementsforall6substances,includingtherequirementthatleadnotexceed0.1%byweightinhomogeneousmaterials.Wheredesignedtobesolderedathightemperatures,TIPb-Freeproductsaresuitableforuseinspecifiedlead-freeprocesses.
Pb-Free(RoHSExempt):ThiscomponenthasaRoHSexemptionforeither1)lead-basedflip-chipsolderbumpsusedbetweenthedieandpackage,or2)lead-baseddieadhesiveusedbetweenthedieandleadframe.ThecomponentisotherwiseconsideredPb-Free(RoHScompatible)asdefinedabove.
Green(RoHS&noSb/Br):TIdefines\"Green\"tomeanPb-Free(RoHScompatible),andfreeofBromine(Br)andAntimony(Sb)basedflameretardants(BrorSbdonotexceed0.1%byweightinhomogeneousmaterial)
(3)
MSL,PeakTemp.--TheMoistureSensitivityLevelratingaccordingtotheJEDECindustrystandardclassifications,andpeaksoldertemperature.
ImportantInformationandDisclaimer:TheinformationprovidedonthispagerepresentsTI'sknowledgeandbeliefasofthedatethatitisprovided.TIbasesitsknowledgeandbeliefoninformationprovidedbythirdparties,andmakesnorepresentationorwarrantyastotheaccuracyofsuchinformation.Effortsareunderwaytobetterintegrateinformationfromthirdparties.TIhastakenandcontinuestotakereasonablestepstoproviderepresentativeandaccurateinformationbutmaynothaveconducteddestructivetestingorchemicalanalysisonincomingmaterialsandchemicals.TIandTIsuppliersconsidercertaininformationtobeproprietary,andthusCASnumbersandotherlimitedinformationmaynotbeavailableforrelease.
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Addendum-Page1
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PACKAGEMATERIALSINFORMATION
www.ti.com
11-Mar-2008
TAPEANDREELINFORMATION
*Alldimensionsarenominal
Device
PackagePackagePinsTypeDrawingTQFPTQFPTQFPTQFP
PFBPFBPFBPFB
48484848
SPQ
ReelReelDiameterWidth(mm)W1(mm)330.0330.0330.0330.0
16.416.416.416.4
A0(mm)B0(mm)K0(mm)
P1(mm)12.012.012.012.0
WPin1(mm)Quadrant16.016.016.016.0
Q2Q2Q2Q2
ADS8405IBPFBRADS8405IBPFBTADS8405IPFBRADS8405IPFBT
10002501000250
9.69.69.69.6
9.69.69.69.6
1.51.51.51.5
PackMaterials-Page1
元器件交易网www.cecb2b.com
PACKAGEMATERIALSINFORMATION
www.ti.com
11-Mar-2008
*Alldimensionsarenominal
DeviceADS8405IBPFBRADS8405IBPFBTADS8405IPFBRADS8405IPFBT
PackageType
TQFPTQFPTQFPTQFP
PackageDrawing
PFBPFBPFBPFB
Pins48484848
SPQ10002501000250
Length(mm)
346.0346.0346.0346.0
Width(mm)346.0346.0346.0346.0
Height(mm)
33.033.033.033.0
PackMaterials-Page2
元器件交易网www.cecb2b.com MTQF019A – JANUARY 1995 – REVISED JANUARY 1998 MECHANICAL DATA PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK0,5036250,270,170,08M372448130,13 NOM15,50 TYP7,20SQ6,809,20SQ8,800,05 MIN1,050,95Seating Plane0,750,45Gage Plane0,250°–7°121,20 MAX0,084073176/B 10/96NOTES:A.All linear dimensions are in millimeters.B.This drawing is subject to change without notice.C.Falls within JEDEC MS-026POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com
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