Features
•High Performance, Low Power AVR® 8-Bit Microcontroller•Advanced RISC Architecture
–120 Powerful Instructions – Most Single Clock Cycle Execution–32 x 8 General Purpose Working Registers–Fully Static Operation
–Up to 20 MIPS Througput at 20 MHz•
Non-volatile Program and Data Memories
–1K Byte of In-System Programmable Program Memory Flash
Endurance: 10,000 Write/Erase Cycles– Bytes In-System Programmable EEPROM
Endurance: 100,000 Write/Erase Cycles– Bytes Internal SRAM
–Programming Lock for Self-Programming Flash Program and EEPROM Data Security
•
Peripheral Features
–One 8-bit Timer/Counter with Prescaler and Two PWM Channels–4-channel, 10-bit ADC with Internal Voltage Reference
–Programmable Watchdog Timer with Separate On-chip Oscillator–On-chip Analog Comparator•
Special Microcontroller Features
–debugWIRE On-chip Debug System–In-System Programmable via SPI Port–External and Internal Interrupt Sources
–Low Power Idle, ADC Noise Reduction, and Power-down Modes–Enhanced Power-on Reset Circuit
–Programmable Brown-out Detection Circuit–Internal Calibrated Oscillator•I/O and Packages
–8-pin PDIP/SOIC: Six Programmable I/O Lines–20-pad MLF: Six Programmable I/O Lines•Operating Voltage:
–1.8 - 5.5V for ATtiny13V–2.7 - 5.5V for ATtiny13•Speed Grade
–ATtiny13V: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V–ATtiny13: 0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V•Industrial Temperature Range•
Low Power Consumption–Active Mode:
1 MHz, 1.8V: 240µA–Power-down Mode:
< 0.1µA at 1.8V
8-bit Microcontroller with 1K Bytes In-SystemProgrammable FlashATtiny13VATtiny13Rev. 2535G–AVR–01/07 2535G–AVR–01/07元器件交易网www.cecb2b.com
Pin Configurations
Figure 1. Pinout ATtiny13
PDIP/SOIC(PCINT5/RESET/ADC0/dW) PB5(PCINT3/CLKI/ADC3) PB3(PCINT4/ADC2) PB4GND12348765VCCPB2 (SCK/ADC1/T0/PCINT2)PB1 (MISO/AIN1/OC0B/INT0/PCINT1)PB0 (MOSI/AIN0/OC0A/PCINT0)QFN/MLFDNCDNCDNCDNCDNC(PCINT5/RESET/ADC0/dW) PB5(PCINT3/CLKI/ADC3) PB3DNCDNC(PCINT4/ADC2) PB41234520 19 18 17 16NOTE: Bottom pad should be soldered to ground.DNC: Do Not ConnectOverview
The ATtiny13 is a low-power CMOS 8-bit microcontroller based on the AVR enhancedRISC architecture. By executing powerful instructions in a single clock cycle, theATtiny13 achieves throughputs approaching 1 MIPS per MHz allowing the systemdesigner to optimize power consumption versus processing speed.
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DNCDNCGNDDNCDNC6 7 8 9 1015 14 13 12 11VCCPB2 (SCK/ADC1/T0/PCINT2)DNCPB1 (MISO/AIN1/OC0B/INT0/PCINT1)PB0 (MOSI/AIN0/OC0A/PCINT0)元器件交易网www.cecb2b.com
ATtiny13
Block Diagram
Figure 2. Block Diagram
8-BIT DATABUSSTACKPOINTERWATCHDOGOSCILLATORCALIBRATEDINTERNALOSCILLATORSRAMVCCWATCHDOGTIMERMCU CONTROLREGISTERMCU STATUSREGISTERTIMER/COUNTER0TIMING ANDCONTROLPROGRAMCOUNTERGNDPROGRAMFLASHINSTRUCTIONREGISTERGENERALPURPOSEREGISTERSINTERRUPTUNITPROGRAMMINGLOGICINSTRUCTIONDECODERXYZCONTROLLINESALUDATAEEPROMSTATUSREGISTER ADC / ANALOG COMPARATORDATA REGISTERPORT BDATA DIR.REG.PORT BPORT B DRIVERSRESETCLKIPB0-PB53
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The AVR core combines a rich instruction set with 32 general purpose working registers.All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowingtwo independent registers to be accessed in one single instruction executed in one clockcycle. The resulting architecture is more code efficient while achieving throughputs up toten times faster than conventional CISC microcontrollers.
The ATtiny13 provides the following features: 1K byte of In-System ProgrammableFlash, bytes EEPROM, bytes SRAM, 6 general purpose I/O lines, 32 general pur-pose working registers, one 8-bit Timer/Counter with compare modes, Internal andExternal Interrupts, a 4-channel, 10-bit ADC, a programmable Watchdog Timer withinternal Oscillator, and three software selectable power saving modes. The Idle modestops the CPU while allowing the SRAM, Timer/Counter, ADC, Analog Comparator, andInterrupt system to continue functioning. The Power-down mode saves the register con-tents, disabling all chip functions until the next Interrupt or Hardware Reset. The ADCNoise Reduction mode stops the CPU and all I/O modules except ADC, to minimizeswitching noise during ADC conversions.
The device is manufactured using Atmel’s high density non-volatile memory technology.The On-chip ISP Flash allows the Program memory to be re-programmed In-Systemthrough an SPI serial interface, by a conventional non-volatile memory programmer orby an On-chip boot code running on the AVR core.
The ATtiny13 AVR is supported with a full suite of program and system developmenttools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Cir-cuit Emulators, and Evaluation kits.
Pin Descriptions
VCCGND
Port B (PB5..PB0)
Digital supply voltage.Ground.
Port B is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for eachbit). The Port B output buffers have symmetrical drive characteristics with both high sinkand source capability. As inputs, Port B pins that are externally pulled low will sourcecurrent if the pull-up resistors are activated. The Port B pins are tri-stated when a resetcondition becomes active, even if the clock is not running.
Port B also serves the functions of various special features of the ATtiny13 as listed onpage 51.
RESETReset input. A low level on this pin for longer than the minimum pulse length will gener-ate a reset, even if the clock is not running. The minimum pulse length is given in Table12 on page 31. Shorter pulses are not guaranteed to generate a reset.
This documentation contains simple code examples that briefly show how to use variousparts of the device. These code examples assume that the part specific header file isincluded before compilation. Be aware that not all C compiler vendors include bit defini-tions in the header files and interrupt handling in C is compiler dependent. Pleaseconfirm with the C compiler documentation for more details.
About Code Examples
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ATtiny13
AVR CPU Core
Introduction
This section discusses the AVR core architecture in general. The main function of theCPU core is to ensure correct program execution. The CPU must therefore be able toaccess memories, perform calculations, control peripherals, and handle interrupts.Figure 3. Block Diagram of the AVR Architecture
Architectural Overview
Data Bus 8-bitFlashProgramMemoryProgramCounterStatusand ControlInstructionRegister32 x 8GeneralPurposeRegistrersInterruptUnitWatchdogTimerIndirect AddressingInstructionDecoderDirect AddressingALUControl LinesAnalogComparatorI/O Module1DataSRAMI/O Module 2I/O Module nEEPROMI/O LinesIn order to maximize performance and parallelism, the AVR uses a Harvard architecture– with separate memories and buses for program and data. Instructions in the Programmemory are executed with a single level pipelining. While one instruction is being exe-cuted, the next instruction is pre-fetched from the Program memory. This conceptenables instructions to be executed in every clock cycle. The Program memory is In-System Reprogrammable Flash memory.
The fast-access Register File contains 32 x 8-bit general purpose working registers witha single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU)operation. In a typical ALU operation, two operands are output from the Register File,
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the operation is executed, and the result is stored back in the Register File – in oneclock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers forData Space addressing – enabling efficient address calculations. One of the theseaddress pointers can also be used as an address pointer for look up tables in Flash Pro-gram memory. These added function registers are the 16-bit X-, Y-, and Z-register,described later in this section.
The ALU supports arithmetic and logic operations between registers or between a con-stant and a register. Single register operations can also be executed in the ALU. Afteran arithmetic operation, the Status Register is updated to reflect information about theresult of the operation.
Program flow is provided by conditional and unconditional jump and call instructions,able to directly address the whole address space. Most AVR instructions have a single16-bit word format. Every Program memory address contains a 16- or 32-bit instruction.During interrupts and subroutine calls, the return address Program Counter (PC) isstored on the Stack. The Stack is effectively allocated in the general data SRAM, andconsequently the Stack size is only limited by the total SRAM size and the usage of theSRAM. All user programs must initialize the SP in the Reset routine (before subroutinesor interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/Ospace. The data SRAM can easily be accessed through the five different addressingmodes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.A flexible interrupt module has its control registers in the I/O space with an additionalGlobal Interrupt Enable bit in the Status Register. All interrupts have a separate InterruptVector in the Interrupt Vector table. The interrupts have priority in accordance with theirInterrupt Vector position. The lower the Interrupt Vector address, the higher the priority.The I/O memory space contains addresses for CPU peripheral functions as ControlRegisters, SPI, and other I/O functions. The I/O memory can be accessed directly, or asthe Data Space locations following those of the Register File, 0x20 - 0x5F.
ALU – Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 generalpurpose working registers. Within a single clock cycle, arithmetic operations betweengeneral purpose registers or between a register and an immediate are executed. TheALU operations are divided into three main categories – arithmetic, logical, and bit-func-tions. Some implementations of the architecture also provide a powerful multipliersupporting both signed/unsigned multiplication and fractional format. See the “Instruc-tion Set” section for a detailed description.
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Status Register
The Status Register contains information about the result of the most recently executedarithmetic instruction. This information can be used for altering program flow in order toperform conditional operations. Note that the Status Register is updated after all ALUoperations, as specified in the Instruction Set Reference. This will in many casesremove the need for using the dedicated compare instructions, resulting in faster andmore compact code.
The Status Register is not automatically stored when entering an interrupt routine andrestored when returning from an interrupt. This must be handled by software.The AVR Status Register – SREG – is defined as:
BitRead/WriteInitial Value
7IR/W0
6TR/W0
5HR/W0
4SR/W0
3VR/W0
2NR/W0
1ZR/W0
0CR/W0
SREG
•Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individ-ual interrupt enable control is then performed in separate control registers. If the GlobalInterrupt Enable Register is cleared, none of the interrupts are enabled independent ofthe individual interrupt enable settings. The I-bit is cleared by hardware after an interrupthas occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, asdescribed in the instruction set reference.•Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source ordestination for the operated bit. A bit from a register in the Register File can be copiedinto T by the BST instruction, and a bit in T can be copied into a bit in a register in theRegister File by the BLD instruction.•Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry isuseful in BCD arithmetic. See the “Instruction Set Description” for detailed information.•Bit 4 – S: Sign Bit, S = N ⊕ V
The S-bit is always an exclusive or between the Negative Flag N and the Two’s Comple-ment Overflow Flag V. See the “Instruction Set Description” for detailed information.•Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetics. Seethe “Instruction Set Description” for detailed information.•Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. Seethe “Instruction Set Description” for detailed information.•Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the“Instruction Set Description” for detailed information.•Bit 0 – C: Carry Flag
The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruc-tion Set Description” for detailed information.
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General Purpose Register File
The Register File is optimized for the AVR Enhanced RISC instruction set. In order toachieve the required performance and flexibility, the following input/output schemes aresupported by the Register File:••••
One 8-bit output operand and one 8-bit result inputTwo 8-bit output operands and one 8-bit result inputTwo 8-bit output operands and one 16-bit result inputOne 16-bit output operand and one 16-bit result input
Figure 4 shows the structure of the 32 general purpose working registers in the CPU.Figure 4. AVR CPU General Purpose Working Registers
7
0
Addr.
R0 0x00R1R2…R13
GeneralPurposeWorkingRegisters
R14R15R16R17…R26R27R28R29R30R31
0x1A0x1B0x1C0x1D0x1E0x1F
X-register Low ByteX-register High ByteY-register Low ByteY-register High ByteZ-register Low ByteZ-register High Byte
0x0D0x0E0x0F0x100x110x010x02
Most of the instructions operating on the Register File have direct access to all registers,and most of them are single cycle instructions.
As shown in Figure 4, each register is also assigned a Data memory address, mappingthem directly into the first 32 locations of the user Data Space. Although not being phys-ically implemented as SRAM locations, this memory organization provides greatflexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set toindex any register in the file.
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ATtiny13
The X-register, Y-register, and The registers R26..R31 have some added functions to their general purpose usage.Z-registerThese registers are 16-bit address pointers for indirect addressing of the data space.
The three indirect address registers X, Y, and Z are defined as described in Figure 5.
Figure 5. The X-, Y-, and Z-registers
15
X-register
7
R27 (0x1B)
XH
0
7
R26 (0x1A)
XL
00
15
Y-register
7
R29 (0x1D)15
Z-register
7
R31 (0x1F)
YH
0
7
R28 (0x1C)
ZH0
7
R30 (0x1E)
YL00
ZL
0
0
In the different addressing modes these address registers have functions as fixed dis-placement, automatic increment, and automatic decrement (see the instruction setreference for details).
Stack Pointer
The Stack is mainly used for storing temporary data, for storing local variables and forstoring return addresses after interrupts and subroutine calls. The Stack Pointer Regis-ter always points to the top of the Stack. Note that the Stack is implemented as growingfrom higher memory locations to lower memory locations. This implies that a StackPUSH command decreases the Stack Pointer.
The Stack Pointer points to the data SRAM Stack area where the Subroutine and Inter-rupt Stacks are located. This Stack space in the data SRAM is automaticall defined tothe last address in SRAM during power on reset. The Stack Pointer must be set to pointabove 0x60. The Stack Pointer is decremented by one when data is pushed onto theStack with the PUSH instruction, and it is decremented by two when the return addressis pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incre-mented by one when data is popped from the Stack with the POP instruction, and it isincremented by two when data is popped from the Stack with return from subroutineRET or return from interrupt RETI.
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The num-ber of bits actually used is implementation dependent. Note that the data space in someimplementations of the AVR architecture is so small that only SPL is needed. In thiscase, the SPH Register will not be present.
Bit
15SP77
Read/WriteInitial Value
R/W1
14SP66R/W0
13SP55R/W0
12SP44R/W1
11SP33R/W1
10SP22R/W1
9SP11R/W1
8SP00R/W1
SPL
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Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. TheAVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clocksource for the chip. No internal clock division is used.
Figure 6 shows the parallel instruction fetches and instruction executions enabled by theHarvard architecture and the fast access Register File concept. This is the basic pipelin-ing concept to obtain up to 1 MIPS per MHz with the corresponding unique results forfunctions per cost, functions per clocks, and functions per power-unit.Figure 6. The Parallel Instruction Fetches and Instruction Executions
T1T2T3T4clkCPU1st Instruction Fetch1st Instruction Execute2nd Instruction Fetch2nd Instruction Execute3rd Instruction Fetch3rd Instruction Execute4th Instruction FetchFigure 7 shows the internal timing concept for the Register File. In a single clock cyclean ALU operation using two register operands is executed, and the result is stored backto the destination register.
Figure 7. Single Cycle ALU Operation
T1T2T3T4clkCPUTotal Execution TimeRegister Operands FetchALU Operation ExecuteResult Write BackReset and Interrupt Handling
The AVR provides several different interrupt sources. These interrupts and the separateReset Vector each have a separate Program Vector in the Program memory space. Allinterrupts are assigned individual enable bits which must be written logic one togetherwith the Global Interrupt Enable bit in the Status Register in order to enable the interrupt.The lowest addresses in the Program memory space are by default defined as theReset and Interrupt Vectors. The complete list of vectors is shown in “Interrupts” onpage 42. The list also determines the priority levels of the different interrupts. The lowerthe address the higher is the priority level. RESET has the highest priority, and next isINT0 – the External Interrupt Request 0.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interruptsare disabled. The user software can write logic one to the I-bit to enable nested inter-rupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit isautomatically set when a Return from Interrupt instruction – RETI – is executed.
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ATtiny13
There are basically two types of interrupts. The first type is triggered by an event thatsets the Interrupt Flag. For these interrupts, the Program Counter is vectored to theactual Interrupt Vector in order to execute the interrupt handling routine, and hardwareclears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing alogic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while thecorresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remem-bered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one ormore interrupt conditions occur while the Global Interrupt Enable bit is cleared, the cor-responding Interrupt Flag(s) will be set and remembered until the Global InterruptEnable bit is set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present.These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disap-pears before the interrupt is enabled, the interrupt will not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and exe-cute one more instruction before any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt rou-tine, nor restored when returning from an interrupt routine. This must be handled bysoftware.
When using the CLI instruction to disable interrupts, the interrupts will be immediatelydisabled. No interrupt will be executed after the CLI instruction, even if it occurs simulta-neously with the CLI instruction. The following example shows how this can be used toavoid interrupts during the timed EEPROM write sequence..Assembly Code Example
inr16, SREGcli
sbiEECR, EEMPEsbiEECR, EEPEoutSREG, r16
; restore SREG value (I-bit); store SREG value; start EEPROM write
; disable interrupts during timed sequence
C Code Example
char cSREG;
cSREG = SREG;/* store SREG value */
/* disable interrupts during timed sequence */__disable_interrupt();
EECR |= (1< 11 2535G–AVR–01/07 元器件交易网www.cecb2b.com When using the SEI instruction to enable interrupts, the instruction following SEI will beexecuted before any pending interrupts, as shown in this example.Assembly Code Example sei ; set Global Interrupt Enable sleep; enter sleep, waiting for interrupt; note: will enter sleep before any pending ; interrupt(s) C Code Example __enable_interrupt(); /* set Global Interrupt Enable */__sleep(); /* enter sleep, waiting for interrupt */ /* note: will enter sleep before any pending interrupt(s) */ Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cyclesminimum. After four clock cycles the Program Vector address for the actual interrupthandling routine is executed. During this four clock cycle period, the Program Counter ispushed onto the Stack. The vector is normally a jump to the interrupt routine, and thisjump takes three clock cycles. If an interrupt occurs during execution of a multi-cycleinstruction, this instruction is completed before the interrupt is served. If an interruptoccurs when the MCU is in sleep mode, the interrupt execution response time isincreased by four clock cycles. This increase comes in addition to the start-up time fromthe selected sleep mode. A return from an interrupt handling routine takes four clock cycles. During these fourclock cycles, the Program Counter (two bytes) is popped back from the Stack, the StackPointer is incremented by two, and the I-bit in SREG is set. 12 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 AVR Memories This section describes the different memories in the ATtiny13. The AVR architecturehas two main memory spaces, the Data memory and the Program memory space. Inaddition, the ATtiny13 features an EEPROM Memory for data storage. All three memoryspaces are linear and regular. The ATtiny13 contains 1K byte On-chip In-System Reprogrammable Flash memory forprogram storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is orga-nized as 512 x 16. The Flash memory has an endurance of at least 10,000 write/erase cycles. TheATtiny13 Program Counter (PC) is nine bits wide, thus addressing the 512 Programmemory locations. “Memory Programming” on page 103 contains a detailed descriptionon Flash data serial downloading using the SPI pins. Constant tables can be allocated within the entire Program memory address space (seethe LPM – Load Program memory instruction description). Timing diagrams for instruction fetch and execution are presented in “Instruction Execu-tion Timing” on page 10.Figure 8. Program Memory Map In-System Re-programmable Flash Program Memory Program Memory0x00000x01FF13 2535G–AVR–01/07 元器件交易网www.cecb2b.com SRAM Data Memory Figure 9 shows how the ATtiny13 SRAM Memory is organized. The lower 160 Data memory locations address both the Register File, the I/O memoryand the internal data SRAM. The first 32 locations address the Register File, the next locations the standard I/O memory, and the last locations address the internal dataSRAM. The five different addressing modes for the Data memory cover: Direct, Indirect withDisplacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. Inthe Register File, registers R26 to R31 feature the indirect addressing pointer registers.The direct addressing reaches the entire data space. The Indirect with Displacement mode reaches 63 address locations from the baseaddress given by the Y- or Z-register. When using register indirect addressing modes with automatic pre-decrement and post-increment, the address registers X, Y, and Z are decremented or incremented. The 32 general purpose working registers, I/O Registers, and the bytes of internaldata SRAM in the ATtiny13 are all accessible through all these addressing modes. TheRegister File is described in “General Purpose Register File” on page 8.Figure 9. Data Memory Map Data Memory32 Registers I/O Registers0x0000 - 0x001F0x0020 - 0x005F0x0060Internal SRAM( x 8)0x009FData Memory Access Times This section describes the general access timing concepts for internal memory access.The internal data SRAM access is performed in two clkCPU cycles as described in Figure10. Figure 10. On-chip Data SRAM Access Cycles T1T2T3clkCPUAddressDataWRDataRDCompute AddressAddress validMemory Access InstructionNext Instruction14 ATtiny13 2535G–AVR–01/07 ReadWrite元器件交易网www.cecb2b.com ATtiny13 EEPROM Data Memory The ATtiny13 contains bytes of data EEPROM memory. It is organized as a separatedata space, in which single bytes can be read and written. The EEPROM has an endur-ance of at least 100,000 write/erase cycles. The access between the EEPROM and theCPU is described in the following, specifying the EEPROM Address Registers, theEEPROM Data Register, and the EEPROM Control Register. For a detailed descriptionof Serial data downloading to the EEPROM, see page 107.The EEPROM Access Registers are accessible in the I/O space. The write access times for the EEPROM are given in Table 1. A self-timing function,however, lets the user software detect when the next byte can be written. If the usercode contains instructions that write the EEPROM, some precautions must be taken. Inheavily filtered power supplies, VCC is likely to rise or fall slowly on Power-up/down. Thiscauses the device for some period of time to run at a voltage lower than specified asminimum for the clock frequency used. See “Preventing EEPROM Corruption” on page19 for details on how to avoid problems in these situations. In order to prevent unintentional EEPROM writes, a specific write procedure must be fol-lowed. Refer to “Atomic Byte Programming” on page 17 and “Split Byte Programming”on page 17 for details on this. When the EEPROM is read, the CPU is halted for four clock cycles before the nextinstruction is executed. When the EEPROM is written, the CPU is halted for two clockcycles before the next instruction is executed. EEPROM Address Register – EEARL BitRead/WriteInitial Value 7–R0 6–R0 5EEAR5R/WX 4EEAR4R/WX 3EEAR3R/WX 2EEAR2R/WX 1EEAR1R/WX 0EEAR0R/WX EEARL EEPROM Read/Write Access •Bits 7..6 – Res: Reserved Bits These bits are reserved bits in the ATtiny13 and will always read as zero.•Bits 5..0 – EEAR5..0: EEPROM Address The EEPROM Address Register – EEARL – specifies the EEPROM address in the bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and63. The initial value of EEARL is undefined. A proper value must be written before theEEPROM may be accessed. EEPROM Data Register – EEDR BitRead/WriteInitial Value 7EEDR7R/WX 6EEDR6R/WX 5EEDR5R/WX 4EEDR4R/WX 3EEDR3R/WX 2EEDR2R/WX 1EEDR1R/WX 0EEDR0R/WX EEDR •Bits 7..0 – EEDR7..0: EEPROM Data For the EEPROM write operation the EEDR Register contains the data to be written tothe EEPROM in the address given by the EEARL Register. For the EEPROM read oper-ation, the EEDR contains the data read out from the EEPROM at the address given byEEARL. 15 2535G–AVR–01/07 元器件交易网www.cecb2b.com EEPROM Control Register – EECR BitRead/WriteInitial Value 7–R0 6–R0 5EEPM1R/WX 4EEPM0R/WX 3EERIER/W0 2EEMPER/W0 1EEPER/WX 0EERER/W0 EECR •Bit 7 – Res: Reserved Bit This bit is reserved for future use and will always read as 0 in ATtiny13. For compatibilitywith future AVR devices, always write this bit to zero. After reading, mask out this bit.•Bit 6 – Res: Reserved Bit This bit is reserved in the ATtiny13 and will always read as zero.•Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits The EEPROM Programming mode bits setting defines which programming action thatwill be triggered when writing EEPE. It is possible to program data in one atomic opera-tion (erase the old value and program the new value) or to split the Erase and Writeoperations in two different operations. The Programming times for the different modesare shown in Table 1. While EEPE is set, any write to EEPMn will be ignored. Duringreset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming.Table 1. EEPROM Mode Bits EEPM10011 EEPM00101 Programming Time 3.4 ms1.8 ms1.8 ms– Operation Erase and Write in one operation (Atomic Operation)Erase OnlyWrite Only Reserved for future use •Bit 3 – EERIE: EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set.Writing EERIE to zero disables the interrupt. The EEPROM Ready Interrupt generates aconstant interrupt when Non-volatile memory is ready for programming.•Bit 2 – EEMPE: EEPROM Master Program Enable The EEMPE bit determines whether writing EEPE to one will have effect or not.When EEMPE is set, setting EEPE within four clock cycles will program the EEPROM atthe selected address. If EEMPE is zero, setting EEPE will have no effect. When EEMPEhas been written to one by software, hardware clears the bit to zero after four clockcycles. •Bit 1 – EEPE: EEPROM Program Enable The EEPROM Program Enable Signal EEPE is the programming enable signal to theEEPROM. When EEPE is written, the EEPROM will be programmed according to theEEPMn bits setting. The EEMPE bit must be written to one before a logical one is writ-ten to EEPE, otherwise no EEPROM write takes place. When the write access time haselapsed, the EEPE bit is cleared by hardware. When EEPE has been set, the CPU ishalted for two cycles before the next instruction is executed.•Bit 0 – EERE: EEPROM Read Enable The EEPROM Read Enable Signal – EERE – is the read strobe to the EEPROM. Whenthe correct address is set up in the EEARL Register, the EERE bit must be written to 16 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 one to trigger the EEPROM read. The EEPROM read access takes one instruction, andthe requested data is available immediately. When the EEPROM is read, the CPU ishalted for four cycles before the next instruction is executed. The user should poll theEEPE bit before starting the read operation. If a write operation is in progress, it is nei-ther possible to read the EEPROM, nor to change the EEARL Register. Atomic Byte Programming Using Atomic Byte Programming is the simplest mode. When writing a byte to theEEPROM, the user must write the address into the EEARL Register and data into EEDRRegister. If the EEPMn bits are zero, writing EEPE (within four cycles after EEMPE iswritten) will trigger the erase/write operation. Both the erase and write cycle are done inone operation and the total programming time is given in Table 1. The EEPE bit remainsset until the erase and write operations are completed. While the device is busy withprogramming, it is not possible to do any other EEPROM operations. It is possible to split the erase and write cycle in two different operations. This may beuseful if the system requires short access time for some limited period of time (typicallyif the power supply voltage falls). In order to take advantage of this method, it is requiredthat the locations to be written have been erased before the write operation. But sincethe erase and write operations are split, it is possible to do the erase operations whenthe system allows doing time-critical operations (typically after Power-up). To erase a byte, the address must be written to EEARL. If the EEPMn bits are 0b01,writing the EEPE (within four cycles after EEMPE is written) will trigger the erase opera-tion only (programming time is given in Table 1). The EEPE bit remains set until theerase operation completes. While the device is busy programming, it is not possible todo any other EEPROM operations. To write a location, the user must write the address into EEARL and the data into EEDR.If the EEPMn bits are 0b10, writing the EEPE (within four cycles after EEMPE is written)will trigger the write operation only (programming time is given in Table 1). The EEPE bitremains set until the write operation completes. If the location to be written has not beenerased before write, the data that is stored must be considered as lost. While the deviceis busy with programming, it is not possible to do any other EEPROM operations.The calibrated Oscillator is used to time the EEPROM accesses. Make sure the Oscilla-tor frequency is within the requirements described in “Oscillator Calibration Register –OSCCAL” on page 23. Split Byte Programming Erase Write 17 2535G–AVR–01/07 元器件交易网www.cecb2b.com The following code examples show one assembly and one C function for erase, write, oratomic write of the EEPROM. The examples assume that interrupts are controlled (e.g.,by disabling interrupts globally) so that no interrupts will occur during execution of thesefunctions. Assembly Code Example EEPROM_write: ; Wait for completion of previous writesbic EECR,EEPErjmp EEPROM_write ; Set Programming modeldiout r16, (0< ; Write data (r16) to data registerout EEDR,r16 ; Write logical one to EEMPEsbi EECR,EEMPE ; Start eeprom write by setting EEPEsbi EECR,EEPEret C Code Example void EEPROM_write(unsigned char ucAddress, unsigned char ucData){ /* Wait for completion of previous write */while(EECR & (1< /* Set up address and data registers */EEARL = ucAddress;EEDR = ucData; /* Write logical one to EEMPE */EECR |= (1< ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 The next code examples show assembly and C functions for reading the EEPROM. Theexamples assume that interrupts are controlled so that no interrupts will occur duringexecution of these functions.Assembly Code Example EEPROM_read: ; Wait for completion of previous writesbic EECR,EEPErjmp EEPROM_read ; Set up address (r17) in address registerout EEARL, r17 ; Start eeprom read by writing EEREsbi EECR,EERE ; Read data from data registerin r16,EEDRret C Code Example unsigned char EEPROM_read(unsigned char ucAddress){ /* Wait for completion of previous write */while(EECR & (1< /* Start eeprom read by writing EERE */EECR |= (1< Preventing EEPROM Corruption During periods of low VCC, the EEPROM data can be corrupted because the supply volt-age is too low for the CPU and the EEPROM to operate properly. These issues are thesame as for board level systems using EEPROM, and the same design solutions shouldbe applied. An EEPROM data corruption can be caused by two situations when the voltage is toolow. First, a regular write sequence to the EEPROM requires a minimum voltage tooperate correctly. Secondly, the CPU itself can execute instructions incorrectly, if thesupply voltage is too low. EEPROM data corruption can easily be avoided by following this designrecommendation: Keep the AVR RESET active (low) during periods of insufficient power supply voltage.This can be done by enabling the internal Brown-out Detector (BOD). If the detectionlevel of the internal BOD does not match the needed detection level, an external lowVCC reset protection circuit can be used. If a reset occurs while a write operation is inprogress, the write operation will be completed provided that the power supply voltage issufficient. 19 2535G–AVR–01/07 元器件交易网www.cecb2b.com I/O Memory The I/O space definition of the ATtiny13 is shown in “Register Summary” on page 159.All ATtiny13 I/Os and peripherals are placed in the I/O space. All I/O locations may beaccessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data betweenthe 32 general purpose working registers and the I/O space. I/O Registers within theaddress range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instruc-tions. In these registers, the value of single bits can be checked by using the SBIS andSBIC instructions. Refer to the instruction set section for more details. When using theI/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used.When addressing I/O Registers as data space using LD and ST instructions, 0x20 mustbe added to these addresses. For compatibility with future devices, reserved bits should be written to zero if accessed.Reserved I/O memory addresses should never be written. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlikemost other AVRs, the CBI and SBI instructions will only operate on the specified bit, andcan therefore be used on registers containing such Status Flags. The CBI and SBIinstructions work with registers 0x00 to 0x1F only. The I/O and Peripherals Control Registers are explained in later sections. 20 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 System Clock and Clock Options Clock Systems and their Figure 11 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, theDistribution clocks to modules not being used can be halted by using different sleep modes, asdescribed in “Power Management and Sleep Modes” on page 27. The clock systemsare detailed below. Figure 11. Clock Distribution ADCGeneral I/OModulesCPU CoreRAMFlash andEEPROMclkI/OclkADCAVR ClockControl UnitclkCPUclkFLASHReset LogicWatchdog TimerSource clockClockMultiplexerWatchdog clockWatchdogOscillatorExternal ClockCalibrated RCOscillatorCPU Clock – clkCPU The CPU clock is routed to parts of the system concerned with operation of the AVRcore. Examples of such modules are the General Purpose Register File, the Status Reg-ister and the Data memory holding the Stack Pointer. Halting the CPU clock inhibits thecore from performing general operations and calculations. The I/O clock is used by the majority of the I/O modules, like Timer/Counter. The I/Oclock is also used by the External Interrupt module, but note that some external inter-rupts are detected by asynchronous logic, allowing such interrupts to be detected even ifthe I/O clock is halted. The Flash clock controls operation of the Flash interface. The Flash clock is usuallyactive simultaneously with the CPU clock. The ADC is provided with a dedicated clock domain. This allows halting the CPU andI/O clocks in order to reduce noise generated by digital circuitry. This gives more accu-rate ADC conversion results. I/O Clock – clkI/O Flash Clock – clkFLASHADC Clock – clkADC 21 2535G–AVR–01/07 元器件交易网www.cecb2b.com Clock Sources The device has the following clock source options, selectable by Flash Fuse bits asshown below. The clock from the selected source is input to the AVR clock generator,and routed to the appropriate modules.Table 2. Device Clocking Options Select(1) Device Clocking OptionCalibrated Internal RC OscillatorExternal Clock 128 kHz Internal OscillatorNote: 1.For all fuses “1” means unprogrammed while “0” means programmed. CKSEL1..001, 100011 The various choices for each clocking option is given in the following sections. When theCPU wakes up from Power-down or Power-save, the selected clock source is used totime the start-up, ensuring stable Oscillator operation before instruction execution starts.When the CPU starts from reset, there is an additional delay allowing the power to reacha stable level before commencing normal operation. The Watchdog Oscillator is usedfor timing this real-time part of the start-up time. The number of WDT Oscillator cyclesused for each time-out is shown in Table 3.Table 3. Number of Watchdog Oscillator Cycles Typ Time-out 4 ms ms Number of Cycles 5128K (8,192) Default Clock Source The device is shipped with CKSEL = “10”, SUT = “10”, and CKDIV8 programmed. Thedefault clock source setting is therefore the Internal RC Oscillator running at 9.6 MHzwith longest start-up time and an initial system clock prescaling of 8. This default settingensures that all users can make their desired clock source setting using an In-System orHigh-voltage Programmer. 22 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 Calibrated Internal RC Oscillator The calibrated internal RC Oscillator provides an 9.6 MHz or 4.8 MHz clock. The fre-quency is the nominal value at 3V and 25°C. If the frequency exceeds the specificationof the device (depends on VCC), the CKDIV8 Fuse must be programmed in order todivide the internal frequency by 8 during start-up. See “System Clock Prescaler” onpage 25. for more details. This clock may be selected as the system clock by program-ming the CKSEL Fuses as shown in Table 4. If selected, it will operate with no externalcomponents. During reset, hardware loads the calibration byte into the OSCCAL Regis-ter and thereby automatically calibrates the RC Oscillator. At 3V and 25°C, thiscalibration gives a frequency within ± 10% of the nominal frequency. Using calibrationmethods as described in application notes available at www.atmel.com/avr it is possibleto achieve ± 3% accuracy at any given VCC and Temperature. When this Oscillator isused as the chip clock, the Watchdog Oscillator will still be used for the Watchdog Timerand for the Reset Time-out. For more information on the pre-programmed calibrationvalue, see the section “Calibration Byte” on page 106.Table 4. Internal Calibrated RC Oscillator Operating Modes CKSEL1..0 10(1)01 Note: 1.The device is shipped with this option selected. Nominal Frequency 9.6 MHz4.8 MHz When this Oscillator is selected, start-up times are determined by the SUT Fuses asshown in Table 5.. Table 5. Start-up Times for the Internal Calibrated RC Oscillator Clock Selection SUT1..0000110(1)11Note: Start-up Time from Power-down 6 CK6 CK6 CK Additional Delay from Reset (VCC = 5.0V) 14CK14CK + 4 ms14CK + msReserved 1.The device is shipped with this option selected. Recommended UsageBOD enabledFast rising powerSlowly rising power Oscillator Calibration Register – OSCCAL BitRead/WriteInitial Value 7–R0 6CAL6R/W 5CAL5R/W 4CAL4R/W 3CAL3R/W 2CAL2R/W 1CAL1R/W 0CAL0R/W OSCCAL Device Specific Calibration Value •Bit 7 – Res: Reserved Bit This bit is reserved bit in the ATtiny13 and will always read as zero.•Bits 6..0 – CAL6..0: Oscillator Calibration Value Writing the calibration byte to this address will trim the internal Oscillator to remove pro-cess variations from the Oscillator frequency. This is done automatically during ChipReset. When OSCCAL is zero, the lowest available frequency is chosen. Writing non-zero values to this register will increase the frequency of the internal Oscillator. Writing0x7F to the register gives the highest available frequency. The calibrated Oscillator isused to time EEPROM and Flash access. If EEPROM or Flash is written, do not cali-brate to more than 10% above the nominal frequency. Otherwise, the EEPROM or Flash 23 2535G–AVR–01/07 元器件交易网www.cecb2b.com write may fail. Note that the Oscillator is intended for calibration to 9.6 MHz or 4.8 MHz.Tuning to other values is not guaranteed, as indicated in Table 6. Avoid changing the calibration value in large steps when calibrating the calibrated inter-nal RC Oscillator to ensure stable operation of the MCU. A variation in frequency ofmore than 2% from one cycle to the next can lead to unpredictable behavior. Changes inOSCCAL-register should not exceed 0x20 for each calibration.Table 6. Internal RC Oscillator Frequency Range OSCCAL Value 0x000x3F0x7F Min Frequency in Percentage of Nominal Frequency 50%75%100% Max Frequency in Percentage of Nominal Frequency 100%150%200% External Clock To drive the device from an external clock source, CLKI should be driven as shown inFigure 12. To run the device on an external clock, the CKSEL Fuses must be pro-grammed to “00”. Figure 12. External Clock Drive Configuration EXTERNALCLOCKSIGNALCLKIGNDWhen this clock source is selected, start-up times are determined by the SUT Fuses asshown in Table 7. Table 7. Start-up Times for the External Clock Selection SUT1..000011011 Start-up Time from Power-down and Power-save 6 CK6 CK6 CK Additional Delay from Reset 14CK14CK + 4 ms14CK + msReserved Recommended UsageBOD enabledFast rising powerSlowly rising power When applying an external clock, it is required to avoid sudden changes in the appliedclock frequency to ensure stable operation of the MCU. A variation in frequency of morethan 2% from one clock cycle to the next can lead to unpredictable behavior. It isrequired to ensure that the MCU is kept in Reset during such changes in the clockfrequency. Note that the System Clock Prescaler can be used to implement run-time changes ofthe internal clock frequency while still ensuring stable operation. Refer to “System ClockPrescaler” on page 25 for details. 24 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 128 kHz Internal Oscillator The 128 kHz internal Oscillator is a low power Oscillator providing a clock of 128 kHz.The frequency is nominal at 3V and 25°C. This clock may be select as the system clockby programming the CKSEL Fuses to “11”. When this clock source is selected, start-up times are determined by the SUT Fuses asshown in Table 8. Table 8. Start-up Times for the 128 kHz Internal Oscillator SUT1..000011011 Start-up Time from Power-down and Power-save 6 CK6 CK6 CK Additional Delay from Reset 14CK14CK + 4 ms14CK + msReserved Recommended UsageBOD enabledFast rising powerSlowly rising power System Clock Prescaler The ATtiny13 system clock can be divided by setting the Clock Prescale Register –CLKPR. This feature can be used to decrease power consumption when the require-ment for processing power is low. This can be used with all clock source options, and itwill affect the clock frequency of the CPU and all synchronous peripherals. clkI/O, clkADC,clkCPU, and clkFLASH are divided by a factor as shown in Table 9. BitRead/WriteInitial Value 7 CLKPCE Clock Prescale Register – CLKPR 6 – 5 – 4 – 3 CLKPS3 2 CLKPS2 1 CLKPS1 0 CLKPS0 CLKPR R/W0 R0 R0 R0 R/WR/WR/WR/W See Bit Description •Bit 7 – CLKPCE: Clock Prescaler Change Enable The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. TheCLKPCE bit is only updated when the other bits in CLKPR are simultaneously written tozero. CLKPCE is cleared by hardware four cycles after it is written or when the CLKPSbits are written. Rewriting the CLKPCE bit within this time-out period does neitherextend the time-out period, nor clear the CLKPCE bit.•Bits 6..4 – Res: Reserved Bits These bits are reserved bits in the ATtiny13 and will always read as zero.•Bits 3..0 – CLKPS3..0: Clock Prescaler Select Bits 3 - 0 These bits define the division factor between the selected clock source and the internalsystem clock. These bits can be written run-time to vary the clock frequency to suit theapplication requirements. As the divider divides the master clock input to the MCU, thespeed of all synchronous peripherals is reduced when a division factor is used. The divi-sion factors are given in Table 9. To avoid unintentional changes of clock frequency, a special write procedure must befollowed to change the CLKPS bits: 1.Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero.2.Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE. Interrupts must be disabled when changing prescaler setting to make sure the write pro-cedure is not interrupted. 25 2535G–AVR–01/07 元器件交易网www.cecb2b.com The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unpro-grammed, the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bitsare reset to “0011”, giving a division factor of eight at start up. This feature should beused if the selected clock source has a higher frequency than the maximum frequencyof the device at the present operating conditions. Note that any value can be written tothe CLKPS bits regardless of the CKDIV8 Fuse setting. The Application software mustensure that a sufficient division factor is chosen if the selected clock source has a higherfrequency than the maximum frequency of the device at the present operating condi-tions. The device is shipped with the CKDIV8 Fuse programmed.Table 9. Clock Prescaler Select CLKPS3 0000000011111111 CLKPS2 0000111100001111 CLKPS1 0011001100110011 CLKPS0 0101010101010101 Clock Division Factor 12481632128256ReservedReservedReservedReservedReservedReservedReserved Switching Time When switching between prescaler settings, the System Clock Prescaler ensures thatno glitches occur in the clock system and that no intermediate frequency is higher thanneither the clock frequency corresponding to the previous setting, nor the clock fre-quency corresponding to the new setting. The ripple counter that implements the prescaler runs at the frequency of the undividedclock, which may be faster than the CPU’s clock frequency. Hence, it is not possible todetermine the state of the prescaler – even if it were readable, and the exact time ittakes to switch from one clock division to another cannot be exactly predicted. From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2*T2before the new clock frequency is active. In this interval, 2 active clock edges are pro-duced. Here, T1 is the previous clock period, and T2 is the period corresponding to thenew prescaler setting. 26 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 Power Management and Sleep Modes The high performance and industry leading code efficiency makes the AVR microcon-trollers an ideal choice for low power applications. Sleep modes enable the application to shut down unused modules in the MCU, therebysaving power. The AVR provides various sleep modes allowing the user to tailor thepower consumption to the application’s requirements. To enter any of the three sleep modes, the SE bit in MCUCR must be written to logicone and a SLEEP instruction must be executed. The SM1..0 bits in the MCUCR Regis-ter select which sleep mode (Idle, ADC Noise Reduction, or Power-down) will beactivated by the SLEEP instruction. See Table 10 for a summary. If an enabled interruptoccurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then haltedfor four cycles in addition to the start-up time, executes the interrupt routine, andresumes execution from the instruction following SLEEP. The contents of the RegisterFile and SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector. Figure 11 on page 21 presents the different clock systems in the ATtiny13, and their dis-tribution. The figure is helpful in selecting an appropriate sleep mode. MCU Control Register – MCUCR The MCU Control Register contains control bits for power management. BitRead/WriteInitialValue 7–R0 6PUDR/W0 5SER/W0 4SM1R/W0 3SM0R/W0 2—R0 1ISC01R/W0 0ISC00R/W0 MCUCR •Bit 5 – SE: Sleep Enable The SE bit must be written to logic one to make the MCU enter the sleep mode when theSLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it isthe programmer’s purpose, it is recommended to write the Sleep Enable (SE) bit to onejust before the execution of the SLEEP instruction and to clear it immediately after wak-ing up. •Bits 4, 3 – SM1..0: Sleep Mode Select Bits 2..0 These bits select between the three available sleep modes as shown in Table 10.Table 10. Sleep Mode Select SM10011 SM00101 Sleep ModeIdle ADC Noise ReductionPower-downReserved •Bit 2 – Res: Reserved Bit This bit is a reserved bit in the ATtiny13 and will always read as zero. 27 2535G–AVR–01/07 元器件交易网www.cecb2b.com Idle Mode When the SM1..0 bits are written to 00, the SLEEP instruction makes the MCU enterIdle mode, stopping the CPU but allowing Analog Comparator, ADC, Timer/Counter,Watchdog, and the interrupt system to continue operating. This sleep mode basicallyhalts clkCPU and clkFLASH, while allowing the other clocks to run. Idle mode enables the MCU to wake up from external triggered interrupts as well asinternal ones like the Timer Overflow. If wake-up from the Analog Comparator interruptis not required, the Analog Comparator can be powered down by setting the ACD bit inthe Analog Comparator Control and Status Register – ACSR. This will reduce powerconsumption in Idle mode. If the ADC is enabled, a conversion starts automaticallywhen this mode is entered. ADC Noise Reduction Mode When the SM1..0 bits are written to 01, the SLEEP instruction makes the MCU enterADC Noise Reduction mode, stopping the CPU but allowing the ADC, the external inter-rupts, and the Watchdog to continue operating (if enabled). This sleep mode halts clkI/O,clkCPU, and clkFLASH, while allowing the other clocks to run. This improves the noise environment for the ADC, enabling higher resolution measure-ments. If the ADC is enabled, a conversion starts automatically when this mode isentered. Apart form the ADC Conversion Complete interrupt, only an External Reset, aWatchdog Reset, a Brown-out Reset, an SPM/EEPROM ready interrupt, an externallevel interrupt on INT0 or a pin change interrupt can wake up the MCU from ADC NoiseReduction mode. Power-down Mode When the SM1..0 bits are written to 10, the SLEEP instruction makes the MCU enterPower-down mode. In this mode, the Oscillator is stopped, while the external interrupts,and the Watchdog continue operating (if enabled). Only an External Reset, a WatchdogReset, a Brown-out Reset, an external level interrupt on INT0, or a pin change interruptcan wake up the MCU. This sleep mode halts all generated clocks, allowing operation ofasynchronous modules only. Note that if a level triggered interrupt is used for wake-up from Power-down mode, thechanged level must be held for some time to wake up the MCU. Refer to “External Inter-rupts” on page for details. Table 11. Active Clock Domains and Wake-up Sources in the Different Sleep Modes Active Clock Domains OscillatorsMain Clock Source EnabledWake-up Sources INT0 and Pin ChangeSleep ModeIdleADC NoiseReductionPower-downNote: XXX XX XX(1)X(1) XX XX X 1.For INT0, only level interrupt. 28 ATtiny13 2535G–AVR–01/07 Watchdog InterruptXXX SPM/EEPROMReadyOther I/OclkFLASHclkADCclkCPUADCclkIO元器件交易网www.cecb2b.com ATtiny13 Minimizing Power Consumption There are several issues to consider when trying to minimize the power consumption inan AVR controlled system. In general, sleep modes should be used as much as possi-ble, and the sleep mode should be selected so that as few as possible of the device’sfunctions are operating. All functions not needed should be disabled. In particular, thefollowing modules may need special consideration when trying to achieve the lowestpossible power consumption. If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC shouldbe disabled before entering any sleep mode. When the ADC is turned off and on again,the next conversion will be an extended conversion. Refer to “Analog to Digital Con-verter” on page 80 for details on ADC operation. When entering Idle mode, the Analog Comparator should be disabled if not used. Whenentering ADC Noise Reduction mode, the Analog Comparator should be disabled. In theother sleep modes, the Analog Comparator is automatically disabled. However, if theAnalog Comparator is set up to use the Internal Voltage Reference as input, the AnalogComparator should be disabled in all sleep modes. Otherwise, the Internal Voltage Ref-erence will be enabled, independent of sleep mode. Refer to “Analog Comparator” onpage 77 for details on how to configure the Analog Comparator. If the Brown-out Detector is not needed in the application, this module should be turnedoff. If the Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled inall sleep modes, and hence, always consume power. In the deeper sleep modes, thiswill contribute significantly to the total current consumption. Refer to “Brown-out Detec-tion” on page 33 for details on how to configure the Brown-out Detector. The Internal Voltage Reference will be enabled when needed by the Brown-out Detec-tion, the Analog Comparator or the ADC. If these modules are disabled as described inthe sections above, the internal voltage reference will be disabled and it will not be con-suming power. When turned on again, the user must allow the reference to start upbefore the output is used. If the reference is kept on in sleep mode, the output can beused immediately. Refer to “Internal Voltage Reference” on page 35 for details on thestart-up time. If the Watchdog Timer is not needed in the application, this module should be turned off.If the Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence,always consume power. In the deeper sleep modes, this will contribute significantly tothe total current consumption. Refer to “Interrupts” on page 42 for details on how to con-figure the Watchdog Timer. When entering a sleep mode, all port pins should be configured to use minimum power.The most important thing is then to ensure that no pins drive resistive loads. In sleepmodes where both the I/O clock (clkI/O) and the ADC clock (clkADC) are stopped, theinput buffers of the device will be disabled. This ensures that no power is consumed bythe input logic when not needed. In some cases, the input logic is needed for detectingwake-up conditions, and it will then be enabled. Refer to the section “Digital InputEnable and Sleep Modes” on page 47 for details on which pins are enabled. If the inputbuffer is enabled and the input signal is left floating or has an analog signal level close toVCC/2, the input buffer will use excessive power. For analog input pins, the digital input buffer should be disabled at all times. An analogsignal level close to VCC/2 on an input pin can cause significant current even in activemode. Digital input buffers can be disabled by writing to the Digital Input Disable Regis-ter (DIDR0). Refer to “Digital Input Disable Register 0 – DIDR0” on page 79 for details. Analog to Digital Converter Analog Comparator Brown-out Detector Internal Voltage Reference Watchdog Timer Port Pins 29 2535G–AVR–01/07 元器件交易网www.cecb2b.com System Control and Reset Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts exe-cution from the Reset Vector. The instruction placed at the Reset Vector must be aRJMP – Relative Jump – instruction to the reset handling routine. If the program neverenables an interrupt source, the Interrupt Vectors are not used, and regular programcode can be placed at these locations. The circuit diagram in Figure 13 shows the resetlogic. Table 12 defines the electrical parameters of the reset circuitry. The I/O ports of the AVR are immediately reset to their initial state when a reset sourcegoes active. This does not require any clock source to be running. After all reset sources have gone inactive, a delay counter is invoked, stretching theinternal reset. This allows the power to reach a stable level before normal operationstarts. The time-out period of the delay counter is defined by the user through the SUTand CKSEL Fuses. The different selections for the delay period are presented in “ClockSources” on page 22. Reset Sources The ATtiny13 has four sources of reset:•••• Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (VPOT). External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length. Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the Watchdog is enabled. Brown-out Reset. The MCU is reset when the supply voltage VCC is below the Brown-out Reset threshold (VBOT) and the Brown-out Detector is enabled. 30 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 Figure 13. Reset Logic DATA BUSMCU StatusRegister (MCUSR)PORFBORFEXTRFWDRFPower-on ResetCircuitBODLEVEL [1..0]Pull-up ResistorSPIKEFILTERBrown-outReset CircuitWatchdogOscillatorClockGeneratorCKDelay CountersTIMEOUTCKSEL[1:0]SUT[1:0]Table 12. Reset Characteristics Symbol ParameterPower-on Reset Threshold Voltage (rising) Power-on Reset Threshold Voltage (falling)(1) RESET Pin Threshold Voltage Minimum pulse width on RESET PinCondition Min Typ1.2 TA = -40 - 85°C 1.1 TA = -40 - 85°CVCC = 1.8V - 5.5VVCC = 1.8V - 5.5V 0.2 VCC 0.77 0.9 VCC2.5 VµsV Max UnitsV VPOT VRSTtRSTNotes: 1.The Power-on Reset will not work unless the supply voltage has been below VPOT (falling) 31 2535G–AVR–01/07 元器件交易网www.cecb2b.com Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detec-tion level is defined in Table 12. The POR is activated whenever VCC is below thedetection level. The POR circuit can be used to trigger the Start-up Reset, as well as todetect a failure in supply voltage. A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reach-ing the Power-on Reset threshold voltage invokes the delay counter, which determineshow long the device is kept in RESET after VCC rise. The RESET signal is activatedagain, without any delay, when VCC decreases below the detection level.Figure 14. MCU Start-up, RESET Tied to VCC VCCVPOTRESETVRSTTIME-OUTtTOUTINTERNALRESETFigure 15. MCU Start-up, RESET Extended ExternallyVCCVPOTRESETVRSTTIME-OUTtTOUTINTERNALRESET32 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 External Reset An External Reset is generated by a low level on the RESET pin if enabled. Resetpulses longer than the minimum pulse width (see Table 12) will generate a reset, even ifthe clock is not running. Shorter pulses are not guaranteed to generate a reset. Whenthe applied signal reaches the Reset Threshold Voltage – VRST – on its positive edge,the delay counter starts the MCU after the Time-out period – tTOUT – has expired.Figure 16. External Reset During Operation CCBrown-out Detection ATtiny13 has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCC levelduring operation by comparing it to a fixed trigger level. The trigger level for the BODcan be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensurespike free Brown-out Detection. The hysteresis on the detection level should be inter-preted as VBOT+ = VBOT + VHYST/2 and VBOT- = VBOT - VHYST/2.Table 13. BODLEVEL Fuse Coding(1) BODLEVEL [1..0] Fuses 11100100 Note: Min VBOT Typ VBOT Max VBOT Units BOD Disabled1.82.74.3 V 1.VBOT may be below nominal minimum operating voltage for some devices. For devices where this is the case, the device is tested down to VCC = VBOT during theproduction test. This guarantees that a Brown-out Reset will occur before VCC dropsto a voltage where correct operation of the microcontroller is no longer guaranteed. Table 14. Brown-out Characteristics SymbolVHYSTtBOD Parameter Brown-out Detector HysteresisMin Pulse Width on Brown-out Reset Min Typ502 Max UnitsmVµs When the BOD is enabled, and VCC decreases to a value below the trigger level (VBOT-in Figure 17), the Brown-out Reset is immediately activated. When VCC increases abovethe trigger level (VBOT+ in Figure 17), the delay counter starts the MCU after the Time-out period tTOUT has expired. The BOD circuit will only detect a drop in VCC if the voltage stays below the trigger levelfor longer than tBOD given in Table 14. 33 2535G–AVR–01/07 元器件交易网www.cecb2b.com Figure 17. Brown-out Reset During Operation VCCVBOT-VBOT+RESETTIME-OUTtTOUTINTERNALRESETWatchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle dura-tion. On the falling edge of this pulse, the delay timer starts counting the Time-out periodtTOUT. Refer to page 42 for details on operation of the Watchdog Timer.Figure 18. Watchdog Reset During Operation CCCKMCU Status Register – MCUSRThe MCU Status Register provides information on which reset source caused an MCUReset. BitRead/WriteInitial Value 7–R0 6–R0 5–R0 4–R0 3WDRFR/W 2BORFR/W 1EXTRFR/W 0PORFR/W MCUSR See Bit Description •Bits 7..4 – Res: Reserved Bits These bits are reserved bits in the ATtiny13 and will always read as zero.•Bit 3 – WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or bywriting a logic zero to the flag. •Bit 2 – BORF: Brown-out Reset Flag This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or bywriting a logic zero to the flag. •Bit 1 – EXTRF: External Reset Flag 34 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or bywriting a logic zero to the flag. •Bit 0 – PORF: Power-on Reset Flag This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero tothe flag. To make use of the Reset Flags to identify a reset condition, the user should read andthen reset the MCUSR as early as possible in the program. If the register is clearedbefore another reset occurs, the source of the reset can be found by examining theReset Flags. Internal Voltage Reference Voltage Reference Enable Signals and Start-up Time ATtiny13 features an internal bandgap reference. This reference is used for Brown-outDetection, and it can be used as an input to the Analog Comparator or the ADC.The voltage reference has a start-up time that may influence the way it should be used.The start-up time is given in Table 15. To save power, the reference is not always turnedon. The reference is on during the following situations: 1.When the BOD is enabled (by programming the BODLEVEL [1..0] Fuse).2.When the bandgap reference is connected to the Analog Comparator (by setting the ACBG bit in ACSR).3.When the ADC is enabled. Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, theuser must always allow the reference to start up before the output from the Analog Com-parator or ADC is used. To reduce power consumption in Power-down mode, the usercan avoid the three conditions above to ensure that the reference is turned off beforeentering Power-down mode. Table 15. Internal Voltage Reference Characteristics SymbolVBGtBGIBG Parameter Bandgap reference voltageBandgap reference start-up timeBandgap reference current consumption Min1.0 Typ1.14015 Max1.270 UnitsVµsµA 35 2535G–AVR–01/07 元器件交易网www.cecb2b.com Watchdog Timer ATtiny13 has an Enhanced Watchdog Timer (WDT). The main features are:•Clocked from separate On-chip Oscillator•3 Operating modes –Interrupt –System Reset –Interrupt and System Reset •Selectable Time-out period from 16ms to 8s •Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode Figure 19. Watchdog Timer 128kHzOSCILLATOROSC/2KOSC/4KOSC/8KOSC/16KOSC/32KOSC/KOSC/128KOSC/256KOSC/512KOSC/1024KWATCHDOGRESETWDEWDP0 WDP1WDP2WDP3MCU RESETWDTIFINTERRUPTWDTIEThe Watchdog Timer (WDT) is a timer counting cycles of a separate on-chip 128 kHzoscillator. The WDT gives an interrupt or a system reset when the counter reaches agiven time-out value. In normal operation mode, it is required that the system uses theWDR - Watchdog Timer Reset - instruction to restart the counter before the time-outvalue is reached. If the system doesn't restart the counter, an interrupt or system resetwill be issued. In Interrupt mode, the WDT gives an interrupt when the timer expires. This interrupt canbe used to wake the device from sleep-modes, and also as a general system timer. Oneexample is to limit the maximum time allowed for certain operations, giving an interruptwhen the operation has run longer than expected. In System Reset mode, the WDTgives a reset when the timer expires. This is typically used to prevent system hang-up incase of runaway code. The third mode, Interrupt and System Reset mode, combines theother two modes by first giving an interrupt and then switch to System Reset mode. Thismode will for instance allow a safe shutdown by saving critical parameters before a sys-tem reset. The Watchdog always on (WDTON) fuse, if programmed, will force the Watchdog Timerto System Reset mode. With the fuse programmed the System Reset mode bit (WDE)and Interrupt mode bit (WDTIE) are locked to 1 and 0 respectively. To further ensureprogram security, alterations to the Watchdog set-up must follow timed sequences. Thesequence for clearing WDE and changing time-out configuration is as follows:1.In the same operation, write a logic one to the Watchdog change enable bit (WDCE) and WDE. A logic one must be written to WDE regardless of the previ-ous value of the WDE bit.2.Within the next four clock cycles, write the WDE and Watchdog prescaler bits (WDP) as desired, but with the WDCE bit cleared. This must be done in oneoperation. 36 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 The following code example shows one assembly and one C function for turning off theWatchdog Timer. The example assumes that interrupts are controlled (e.g. by disablinginterrupts globally) so that no interrupts will occur during the execution of thesefunctions. Assembly Code Example(1) WDT_off: ; Turn off global interruptcli ; Reset Watchdog Timerwdr ; Clear WDRF in MCUSRin r16, MCUSR andi r16, (0xff & (0< ; Keep old prescaler setting to prevent unintentional time-outin r16, WDTCR ori r16, (1< C Code Example(1) void WDT_off(void){ __disable_interrupt();__watchdog_reset();/* Clear WDRF in MCUSR */MCUSR &= ~(1< /* Keep old prescaler setting to prevent unintentional time-out */ WDTCR |= (1< 1.The example code assumes that the part specific header file is included. Note: If the Watchdog is accidentally enabled, for example by a runaway pointer orbrown-out condition, the device will be reset and the Watchdog Timer will stay enabled.If the code is not set up to handle the Watchdog, this might lead to an eternal loop oftime-out resets. To avoid this situation, the application software should always clear the 37 2535G–AVR–01/07 元器件交易网www.cecb2b.com Watchdog System Reset Flag (WDRF) and the WDE control bit in the initialisation rou-tine, even if the Watchdog is not in use. The following code example shows one assembly and one C function for changing thetime-out value of the Watchdog Timer.Assembly Code Example(1)WDT_Prescaler_Change: ; Turn off global interruptcli ; Reset Watchdog Timerwdr ; Start timed sequencein r16, WDTCR ori r16, (1< C Code Example(1) void WDT_Prescaler_Change(void){ __disable_interrupt();__watchdog_reset(); /* Start timed sequence */WDTCR |= (1< Note: The Watchdog Timer should be reset before any change of the WDP bits, since achange in the WDP bits can result in a time-out when switching to a shorter time-outperiod. 38 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 Watchdog Timer Control Register - WDTCR BitRead/WriteInitialValue 7WDTIFR/W0 6WDTIER/W0 5WDP3R/W0 4WDCER/W0 3WDER/WX 2WDP2R/W0 1WDP1R/W0 0WDP0R/W0 WDTCR •Bit 7 - WDTIF: Watchdog Timer Interrupt Flag This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer isconfigured for interrupt. WDTIF is cleared by hardware when executing the correspond-ing interrupt handling vector. Alternatively, WDTIF is cleared by writing a logic one to theflag. When the I-bit in SREG and WDTIE are set, the Watchdog Time-out Interrupt isexecuted. •Bit 6 - WDTIE: Watchdog Timer Interrupt Enable When this bit is written to one and the I-bit in the Status Register is set, the WatchdogInterrupt is enabled. If WDE is cleared in combination with this setting, the WatchdogTimer is in Interrupt Mode, and the corresponding interrupt is executed if time-out in theWatchdog Timer occurs. If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. The firsttime-out in the Watchdog Timer will set WDTIF. Executing the corresponding interruptvector will clear WDTIE and WDTIF automatically by hardware (the Watchdog goes toSystem Reset Mode). This is useful for keeping the Watchdog Timer security whileusing the interrupt. To stay in Interrupt and System Reset Mode, WDTIE must be setafter each interrupt. This should however not be done within the interrupt service routineitself, as this might compromise the safety-function of the Watchdog System Resetmode. If the interrupt is not executed before the next time-out, a System Reset will beapplied. Table 16. Watchdog Timer Configuration WDTON(1) 11110Note: WDE0011x WDTIE0101x ModeStoppedInterrupt ModeSystem Reset ModeInterrupt and System Reset ModeSystem Reset Mode Action on Time-outNoneInterruptReset Interrupt, then go to System Reset ModeReset 1.WDTON Fuse set to “0“ means programmed and “1“ means unprogrammed. •Bit 4 - WDCE: Watchdog Change Enable This bit is used in timed sequences for changing WDE and prescaler bits. To clear theWDE bit, and/or change the prescaler bits, WDCE must be set.Once written to one, hardware will clear WDCE after four clock cycles.•Bit 3 - WDE: Watchdog System Reset Enable WDE is overridden by WDRF in MCUSR. This means that WDE is always set whenWDRF is set. To clear WDE, WDRF must be cleared first. This feature ensures multipleresets during conditions causing failure, and a safe start-up after the failure.•Bit 5, 2..0 - WDP3..0: Watchdog Timer Prescaler 3, 2, 1 and 0 39 2535G–AVR–01/07 元器件交易网www.cecb2b.com The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timeris running. The different prescaling values and their corresponding time-out periods areshown in Table 17 on page 41. 40 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 Table 17. Watchdog Timer Prescale Select WDP30000000011111111 WDP20000111100001111 WDP10011001100110011 WDP00101010101010101 Reserved Number of WDT Oscillator Cycles 2K (2048) cycles4K (4096) cycles8K (8192) cycles16K (16384) cycles32K (32768) cyclesK (65536) cycles128K (131072) cycles256K (262144) cycles512K (524288) cycles1024K (1048576) cycles Typical Time-out at VCC = 5.0V 16 ms32 ms ms0.125 s0.25 s0.5 s1.0 s2.0 s4.0 s8.0 s 41 2535G–AVR–01/07 元器件交易网www.cecb2b.com Interrupts This section describes the specifics of the interrupt handling as performed in ATtiny13.For a general explanation of the AVR interrupt handling, refer to “Reset and InterruptHandling” on page 10. Table 18. Reset and Interrupt Vectors VectorNo.123456710 ProgramAddress0x00000x00010x00020x00030x00040x00050x00060x00070x00080x0009 SourceRESETINT0PCINT0TIM0_OVFEE_RDYANA_COMPTIM0_COMPATIM0_COMPBWDTADC Interrupt Definition External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset External Interrupt Request 0Pin Change Interrupt Request 0Timer/Counter OverflowEEPROM ReadyAnalog Comparator Timer/Counter Compare Match ATimer/Counter Compare Match BWatchdog Time-outADC Conversion Complete Interrupt Vectors in ATtiny13 If the program never enables an interrupt source, the Interrupt Vectors are not used, andregular program code can be placed at these locations. The most typical and generalprogram setup for the Reset and Interrupt Vector Addresses in ATtiny13 is: AddressLabelsCode0x00000x00010x00020x00030x00040x00050x00060x00070x00080x0009;0x000A0x000BRAM0x000C0x000D ... RESET:ldiout r16, low(RAMEND); Main program start ; Set Stack Pointer to top of ; Enable interrupts SPL,r16sei rjmprjmprjmprjmprjmprjmprjmprjmprjmprjmp RESETEXT_INT0PCINT0TIM0_OVFEE_RDYANA_COMPTIM0_COMPATIM0_COMPBWATCHDOGADC Comments ; Reset Handler; IRQ0 Handler; PCINT0 Handler ; Timer0 Overflow Handler; EEPROM Ready Handler; Analog Comparator Handler; Timer0 CompareA Handler; Timer0 CompareB Handler; Watchdog Interrupt Handler; ADC Conversion Handler 42 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 I/O Ports Introduction All AVR ports have true Read-Modify-Write functionality when used as general digitalI/O ports. This means that the direction of one port pin can be changed without uninten-tionally changing the direction of any other pin with the SBI and CBI instructions. Thesame applies when changing drive value (if configured as output) or enabling/disablingof pull-up resistors (if configured as input). Each output buffer has symmetrical drivecharacteristics with both high sink and source capability. The pin driver is strong enoughto drive LED displays directly. All port pins have individually selectable pull-up resistorswith a supply-voltage invariant resistance. All I/O pins have protection diodes to bothVCC and Ground as indicated in Figure 20. Refer to “Electrical Characteristics” on page120 for a complete list of parameters.Figure 20. I/O Pin Equivalent Schematic RpuPxnLogicCpinSee Figure\"General Digital I/O\" forDetailsAll registers and bit references in this section are written in general form. A lower case“x” represents the numbering letter for the port, and a lower case “n” represents the bitnumber. However, when using the register or bit defines in a program, the precise formmust be used. For example, PORTB3 for bit no. 3 in Port B, here documented generallyas PORTxn. The physical I/O Registers and bit locations are listed in “Register Descrip-tion for I/O-Ports” on page 53. Three I/O memory address locations are allocated for each port, one each for the DataRegister – PORTx, Data Direction Register – DDRx, and the Port Input Pins – PINx. ThePort Input Pins I/O location is read only, while the Data Register and the Data DirectionRegister are read/write. However, writing a logic one to a bit in the PINx Register, willresult in a toggle in the corresponding bit in the Data Register. In addition, the Pull-upDisable – PUD bit in MCUCR disables the pull-up function for all pins in all ports whenset. Using the I/O port as General Digital I/O is described in “Ports as General Digital I/O” onpage 44. Most port pins are multiplexed with alternate functions for the peripheral fea-tures on the device. How each alternate function interferes with the port pin is describedin “Alternate Port Functions” on page 48. Refer to the individual module sections for afull description of the alternate functions. 43 2535G–AVR–01/07 元器件交易网www.cecb2b.com Note that enabling the alternate function of some of the port pins does not affect the useof the other pins in the port as general digital I/O. Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 21 shows afunctional description of one I/O-port pin, here generically called Pxn.Figure 21. General Digital I/O(1) PUDQDDDxnQCLRRESETWDxRDx1PxnQDPORTxnQCLR0RESETWRxSLEEPSYNCHRONIZERDQDQWPxRRxRPxPINxnLQQclkI/OPUD:SLEEP:clkI/O:PULLUP DISABLESLEEP CONTROLI/O CLOCKWDx:RDx:WRx:RRx:RPx:WPx:WRITE DDRxREAD DDRxWRITE PORTxREAD PORTx REGISTERREAD PORTx PINWRITE PINx REGISTERNote: 1.WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O, SLEEP, and PUD are common to all ports. Configuring the Pin Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in“Register Description for I/O-Ports” on page 53, the DDxn bits are accessed at theDDRx I/O address, the PORTxn bits at the PORTx I/O address, and the PINxn bits atthe PINx I/O address. The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is writtenlogic one, Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is config-ured as an input pin. If PORTxn is written logic one when the pin is configured as an input pin, the pull-upresistor is activated. To switch the pull-up resistor off, PORTxn has to be written logiczero or the pin has to be configured as an output pin. The port pins are tri-stated whenreset condition becomes active, even if no clocks are running. If PORTxn is written logic one when the pin is configured as an output pin, the port pin isdriven high (one). If PORTxn is written logic zero when the pin is configured as an out-put pin, the port pin is driven low (zero). 44 ATtiny13 2535G–AVR–01/07 DATA BUS元器件交易网www.cecb2b.com ATtiny13 Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value ofDDRxn. Note that the SBI instruction can be used to toggle one single bit in a port.When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn,PORTxn} = 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} =0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-upenabled state is fully acceptable, as a high-impedant environment will not notice the dif-ference between a strong high driver and a pull-up. If this is not the case, the PUD bit inthe MCUCR Register can be set to disable all pull-ups in all ports. Switching between input with pull-up and output low generates the same problem. Theuser must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state({DDxn, PORTxn} = 0b10) as an intermediate step.Table 19 summarizes the control signals for the pin value.Table 19. Port Pin Configurations DDxn00011 PORTxn 01101 PUD(in MCUCR) X01XX I/OInputInputInputOutputOutput Pull-upNoYesNoNoNo CommentTri-state (Hi-Z) Pxn will source current if ext. pulled low. Tri-state (Hi-Z)Output Low (Sink)Output High (Source) Switching Between Input and Output Reading the Pin Value Independent of the setting of Data Direction bit DDxn, the port pin can be read throughthe PINxn Register bit. As shown in Figure 21, the PINxn Register bit and the precedinglatch constitute a synchronizer. This is needed to avoid metastability if the physical pinchanges value near the edge of the internal clock, but it also introduces a delay. Figure22 shows a timing diagram of the synchronization when reading an externally appliedpin value. The maximum and minimum propagation delays are denoted tpd,max and tpd,minrespectively. Figure 22. Synchronization when Reading an Externally Applied Pin value SYSTEM CLKINSTRUCTIONSSYNC LATCHPINxnr170x00tpd, maxtpd, min0xFFXXXXXXin r17, PINx45 2535G–AVR–01/07 元器件交易网www.cecb2b.com Consider the clock period starting shortly after the first falling edge of the system clock.The latch is closed when the clock is low, and goes transparent when the clock is high,as indicated by the shaded region of the “SYNC LATCH” signal. The signal value islatched when the system clock goes low. It is clocked into the PINxn Register at the suc-ceeding positive clock edge. As indicated by the two arrows tpd,max and tpd,min, asingle signal transition on the pin will be delayed between ½ and 1½ system clockperiod depending upon the time of assertion. When reading back a software assigned pin value, a nop instruction must be inserted asindicated in Figure 23. The out instruction sets the “SYNC LATCH” signal at the positiveedge of the clock. In this case, the delay tpd through the synchronizer is one systemclock period. Figure 23. Synchronization when Reading a Software Assigned Pin Value SYSTEM CLKr16INSTRUCTIONSSYNC LATCHPINxnr170x00tpd0xFFout PORTx, r16nop0xFFin r17, PINx46 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, anddefine the port pins from 4 to 5 as input with a pull-up assigned to port pin 4. The result-ing pin values are read back again, but as previously discussed, a nop instruction isincluded to be able to read back the value recently assigned to some of the pins.Assembly Code Example(1) ... ; Define pull-ups and set outputs high; Define directions for port pinsldildioutoutnop ; Read port pinsin... r16,PINB r16,(1< C Code Example unsigned char i;... /* Define pull-ups and set outputs high *//* Define directions for port pins */PORTB = (1< 1.For the assembly program, two temporary registers are used to minimize the time from pull-ups are set on pins 0, 1 and 4, until the direction bits are correctly set, defin-ing bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers. Digital Input Enable and Sleep As shown in Figure 21, the digital input signal can be clamped to ground at the input ofModesthe schmitt-trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down mode, Power-save mode, and Standby mode to avoid highpower consumption if some input signals are left floating, or have an analog signal levelclose to VCC/2. SLEEP is overridden for port pins enabled as external interrupt pins. If the external inter-rupt request is not enabled, SLEEP is active also for these pins. SLEEP is alsooverridden by various other alternate functions as described in “Alternate Port Func-tions” on page 48. If a logic high level (“one”) is present on an asynchronous external interrupt pin config-ured as “Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin” while theexternal interrupt is not enabled, the corresponding External Interrupt Flag will be set 47 2535G–AVR–01/07 元器件交易网www.cecb2b.com when resuming from the above mentioned Sleep mode, as the clamping in these sleepmode produces the requested logic change. Unconnected Pins If some pins are unused, it is recommended to ensure that these pins have a definedlevel. Even though most of the digital inputs are disabled in the deep sleep modes asdescribed above, floating inputs should be avoided to reduce current consumption in allother modes where the digital inputs are enabled (Reset, Active mode and Idle mode).The simplest method to ensure a defined level of an unused pin, is to enable the internalpull-up. In this case, the pull-up will be disabled during reset. If low power consumptionduring reset is important, it is recommended to use an external pull-up or pull-down.Connecting unused pins directly to VCC or GND is not recommended, since this maycause excessive currents if the pin is accidentally configured as an output. Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. Figure24 shows how the port pin control signals from the simplified Figure 21 can be overrid-den by alternate functions. The overriding signals may not be present in all port pins, butthe figure serves as a generic description applicable to all port pins in the AVR micro-controller family. 48 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 Figure 24. Alternate Port Functions(1) PUOExnPUOVxnPUD10DDOExnDDOVxnQDDDxnQCLR10PVOExnPVOVxnRESETWDxRDx1Pxn0QD10PORTxnPTOExnWPxWRxRRxDIEOExnDIEOVxnSLEEPSYNCHRONIZERDSETQCLR10RESETRPxQDQPINxnLCLRQCLRQclkI/ODIxnAIOxnPUOExn:PUOVxn:DDOExn:DDOVxn:PVOExn:PVOVxn:DIEOExn:DIEOVxn:SLEEP:PTOExn:Pxn PULL-UP OVERRIDE ENABLEPxn PULL-UP OVERRIDE VALUEPxn DATA DIRECTION OVERRIDE ENABLEPxn DATA DIRECTION OVERRIDE VALUEPxn PORT VALUE OVERRIDE ENABLEPxn PORT VALUE OVERRIDE VALUEPxn DIGITAL INPUT-ENABLE OVERRIDE ENABLEPxn DIGITAL INPUT-ENABLE OVERRIDE VALUESLEEP CONTROLPxn, PORT TOGGLE OVERRIDE ENABLEPUD:WDx:RDx:RRx:WRx:RPx:WPx:clkI/O:DIxn:AIOxn: PULLUP DISABLE WRITE DDRx READ DDRx READ PORTx REGISTER WRITE PORTx READ PORTx PINWRITE PINx I/O CLOCK DIGITAL INPUT PIN n ON PORTx ANALOG INPUT/OUTPUT PIN n ON PORTxNote: 1.WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O, SLEEP, and PUD are common to all ports. All other signals are unique for eachpin. 2535G–AVR–01/07 DATA BUS49 元器件交易网www.cecb2b.com Table 20 summarizes the function of the overriding signals. The pin and port indexesfrom Figure 24 are not shown in the succeeding tables. The overriding signals are gen-erated internally in the modules having the alternate function. Table 20. Generic Description of Overriding Signals for Alternate Functions Signal NamePUOE Full NamePull-up Override Enable Pull-up Override Value Data Direction Override EnableData Direction Override ValuePort Value Override Enable Description If this signal is set, the pull-up enable is controlled by the PUOV signal. If this signal is cleared, the pull-up is enabled when {DDxn, PORTxn, PUD} = 0b010. If PUOE is set, the pull-up is enabled/disabled when PUOV is set/cleared, regardless of the setting of the DDxn, PORTxn, and PUD Register bits. If this signal is set, the Output Driver Enable is controlled by the DDOV signal. If this signal is cleared, the Output driver is enabled by the DDxn Register bit. If DDOE is set, the Output Driver is enabled/disabled when DDOV is set/cleared, regardless of the setting of the DDxn Register bit. If this signal is set and the Output Driver is enabled, the port value is controlled by the PVOV signal. If PVOE is cleared, and the Output Driver is enabled, the port Value is controlled by the PORTxn Register bit. If PVOE is set, the port value is set to PVOV, regardless of the setting of the PORTxn Register bit. If PTOE is set, the PORTxn Register bit is inverted.If this bit is set, the Digital Input Enable is controlled by the DIEOV signal. If this signal is cleared, the Digital Input Enable is determined by MCU state (Normal mode, sleep mode). If DIEOE is set, the Digital Input is enabled/disabled when DIEOV is set/cleared, regardless of the MCU state (Normal mode, sleep mode). This is the Digital Input to alternate functions. In the figure, the signal is connected to the output of the schmitt-trigger but before the synchronizer. Unless the Digital Input is used as a clock source, the module with the alternate function will use its own synchronizer.This is the Analog Input/Output to/from alternate functions. The signal is connected directly to the pad, and can be used bi-directionally. PUOV DDOE DDOV PVOE PVOVPTOEDIEOE Port Value Override ValuePort Toggle Override EnableDigital Input Enable Override Enable Digital Input Enable Override ValueDigital Input DIEOV DI AIO Analog Input/Output The following subsections shortly describe the alternate functions for each port, andrelate the overriding signals to the alternate function. Refer to the alternate functiondescription for further details. 50 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 MCU Control Register – MCUCR BitRead/WriteInitial Value 7–R0 6PUDR/W0 5SER/W0 4SM1R/W0 3SM0R/W0 2–R0 1ISC01R/W0 0ISC00R/W0 MCUCR •Bits 7, 2– Res: Reserved Bits These bits are reserved bits in the ATtiny13 and will always read as zero.•Bit 6 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxnand PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01).See “Configuring the Pin” on page 44 for more details about this feature. Alternate Functions of Port B The Port B pins with alternate function are shown in Table 21.Table 21. Port B Pins Alternate Functions Port PinPB5PB4PB3PB2PB1PB0 Notes: 1.2.3.4. Alternate FunctionRESET/dW/ADC0/PCINT5(1)ADC2/PCINT4(2)ADC3/CLKI/PCINT3(3)SCK/ADC1/T0/PCINT2(4) MISO/AIN1/OC0B/INT0/PCINT1/RXD(5)MOSI/AIN0/OC0A/PCINT0/TXD(6) Reset pin, debugWire I/O, ADC Input channel, or Pin Change Interrupt.ADC Input channel or Pin Change Interrupt. ADC Input channel, Clock Input, or Pin Change Interrupt. Serial Clock Input, Timer/Counter Clock Input, ADC Input Channel 0, or Pin ChangeInterrupt. 5.Serial Data Input, Analog Comparator Negative Input, Output Compare and PWM Output B for Timer/Counter, External Interrupt 0 or Pin Change Interrupt. 6.Serial Data Output, Analog Comparator Positive Input, Output Compare and PWM Output A for Timer/Counter, or Pin Change Interrupt. Table 22 and Table 23 on page 52 relate the alternate functions of Port B to the overrid-ing signals shown in Figure 24 on page 49. 51 2535G–AVR–01/07 元器件交易网www.cecb2b.com Table 22. Overriding Signals for Alternate Functions in PB5..PB3 SignalNamePUOEPUOVDDOEDDOVPVOEPVOVPTOEDIEOEDIEOVDIAIONote: PB5/RESET/ADC0/PCINT5RSTDISBL(1) • DWEN(1)1 RSTDISBL(1) • DWEN(1)debugWire Transmit000 RSTDISBL(1) + (PCINT5 • PCIE + ADC0D)ADC0DPCINT5 Input RESET Input, ADC0 Input PB4/ADC2/PCINT40000000 PCINT4 • PCIE + ADC2DADC2DPCINT4 InputADC2 Input PB3/ADC3/CLKI/PCINT30000000 PCINT3 • PCIE + ADC3DADC3DPCINT3 InputADC3 Input 1.1 when the Fuse is “0” (Programmed). Table 23. Overriding Signals for Alternate Functions in PB2..PB0 SignalNamePUOEPUOVDDOEDDOVPVOEPVOVPTOEDIEOEDIEOVDIAIO PB2/SCK/ADC1/T0/PCINT20000000 PCINT2 • PCIE + ADC1DADC1DT0/INT0/ PCINT2 InputADC1 Input PB1/MISO/AIN1/OC0B/INT0/PCINT10000 OC0B EnableOC0B0 PCINT1 • PCIE + AIN1DAIN1DPCINT1 InputAnalog Comparator Negative Input PB0/MOSI/AIN0/AREF/OC0A/PCINT00000 OC0A Enable OC0A0 PCINT0 • PCIE + AIN0DAIN0DPCINT0 InputAnalog Comparator Positive Input 52 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 Register Description for I/O-Ports Port B Data Register – PORTB BitRead/WriteInitialValue 7 – 6 – 5 PORTB5 4 PORTB4 3 PORTB3 2 PORTB2 1 PORTB1 0 PORTB0 PORTB R0 R0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 Port B Data Direction Register – DDRB BitRead/WriteInitialValue 7 – 6 – 5DDB5R/W0 4DDB4R/W0 3DDB3R/W0 2DDB2R/W0 1DDB1R/W0 0DDB0R/W0 DDRB R0 R0 Port B Input Pins Address – PINB BitRead/WriteInitial Value 7 – 6 – 5PINB5R/WN/A 4PINB4R/WN/A 3PINB3R/WN/A 2PINB2R/WN/A 1PINB1R/WN/A 0PINB0R/WN/A PINB R0 R0 53 2535G–AVR–01/07 元器件交易网www.cecb2b.com External Interrupts The External Interrupts are triggered by the INT0 pin or any of the PCINT5..0 pins.Observe that, if enabled, the interrupts will trigger even if the INT0 or PCINT5..0 pins areconfigured as outputs. This feature provides a way of generating a software interrupt.Pin change interrupts PCI will trigger if any enabled PCINT5..0 pin toggles. The PCMSKRegister control which pins contribute to the pin change interrupts. Pin change interruptson PCINT5..0 are detected asynchronously. This implies that these interrupts can beused for waking the part also from sleep modes other than Idle mode. The INT0 interrupts can be triggered by a falling or rising edge or a low level. This is setup as indicated in the specification for the MCU Control Register – MCUCR. When theINT0 interrupt is enabled and is configured as level triggered, the interrupt will trigger aslong as the pin is held low. Note that recognition of falling or rising edge interrupts onINT0 requires the presence of an I/O clock, described in “Clock Systems and their Distri-bution” on page 21. Low level interrupt on INT0 is detected asynchronously. This impliesthat this interrupt can be used for waking the part also from sleep modes other than Idlemode. The I/O clock is halted in all sleep modes except Idle mode. Note that if a level triggered interrupt is used for wake-up from Power-down, therequired level must be held long enough for the MCU to complete the wake-up to triggerthe level interrupt. If the level disappears before the end of the Start-up Time, the MCUwill still wake up, but no interrupt will be generated. The start-up time is defined by theSUT and CKSEL Fuses as described in “System Clock and Clock Options” on page 21. Pin Change Interrupt Timing An example of timing of a pin change interrupt is shown in Figure 25.Figure 25. Timing of pin change interrupts PCINT(0)LEpin_latD Qpcint_in_(0)pin_syncPCINT(0) in PCMSK(x)0xclkpcint_synpcint_setflagPCIFclkclkPCINT(n)pin_latpin_syncpcint_in_(n)pcint_synpcint_setflagPCIF ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 External Interrupt registers MCU Control Register – MCUCR The External Interrupt Control Register A contains control bits for interrupt sensecontrol. BitRead/WriteInitialValue 7–R0 6PUDR/W0 5SER/W0 4SM1R/W0 3SM0R/W0 2–R0 1ISC01R/W0 0ISC00R/W0 MCUCR •Bits 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0 The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and thecorresponding interrupt mask are set. The level and edges on the external INT0 pin thatactivate the interrupt are defined in Table 24. The value on the INT0 pin is sampledbefore detecting edges. If edge or toggle interrupt is selected, pulses that last longerthan one clock period will generate an interrupt. Shorter pulses are not guaranteed togenerate an interrupt. If low level interrupt is selected, the low level must be held untilthe completion of the currently executing instruction to generate an interrupt.Table 24. Interrupt 0 Sense Control ISC01 ISC000101 Description The low level of INT0 generates an interrupt request.Any logical change on INT0 generates an interrupt request.The falling edge of INT0 generates an interrupt request.The rising edge of INT0 generates an interrupt request. 0011 55 2535G–AVR–01/07 元器件交易网www.cecb2b.com General Interrupt Mask Register – GIMSK BitRead/WriteInitial Value 7–R0 6INT0R/W0 5PCIER/W0 4–R0 3–R0 2–R0 1–R0 0–R0 GIMSK •Bits 7, 4..0 – Res: Reserved Bits These bits are reserved bits in the ATtiny13 and will always read as zero.•Bit 6 – INT0: External Interrupt Request 0 Enable When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 andISC00) in the MCU Control Register (MCUCR) define whether the external interrupt isactivated on rising and/or falling edge of the INT0 pin or level sensed. Activity on the pinwill cause an interrupt request even if INT0 is configured as an output. The correspond-ing interrupt of External Interrupt Request 0 is executed from the INT0 Interrupt Vector.•Bit 5 – PCIE: Pin Change Interrupt Enable When the PCIE bit is set (one) and the I-bit in the Status Register (SREG) is set (one),pin change interrupt is enabled. Any change on any enabled PCINT5..0 pin will causean interrupt. The corresponding interrupt of Pin Change Interrupt Request is executedfrom the PCI Interrupt Vector. PCINT5..0 pins are enabled individually by the PCMSK0Register. General Interrupt Flag Register – GIFR BitRead/WriteInitial Value 7–R0 6INTF0R/W0 5PCIFR/W0 4–R0 3–R0 2–R0 1–R0 0–R0 GIFR •Bits 7, 4..0 – Res: Reserved Bits These bits are reserved bits in the ATtiny13 and will always read as zero.•Bit 6 – INTF0: External Interrupt Flag 0 When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0becomes set (one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), theMCU will jump to the corresponding Interrupt Vector. The flag is cleared when the inter-rupt routine is executed. Alternatively, the flag can be cleared by writing a logical one toit. This flag is always cleared when INT0 is configured as a level interrupt.•Bit 5 – PCIF: Pin Change Interrupt Flag When a logic change on any PCINT5..0 pin triggers an interrupt request, PCIF becomesset (one). If the I-bit in SREG and the PCIE bit in GIMSK are set (one), the MCU willjump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routineis executed. Alternatively, the flag can be cleared by writing a logical one to it. 56 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 Pin Change Mask Register – PCMSK BitRead/WriteInitial Value 7–R0 6–R0 5PCINT5R/W0 4PCINT4R/W0 3PCINT3R/W0 2PCINT2R/W0 1PCINT1R/W0 0PCINT0R/W0 PCMSK •Bits 7, 6 – Res: Reserved Bits These bits are reserved bits in the ATtiny13 and will always read as zero.•Bits 5..0 – PCINT5..0: Pin Change Enable Mask 5..0 Each PCINT5..0 bit selects whether pin change interrupt is enabled on the correspond-ing I/O pin. If PCINT5..0 is set and the PCIE bit in GIMSK is set, pin change interrupt isenabled on the corresponding I/O pin. If PCINT5..0 is cleared, pin change interrupt onthe corresponding I/O pin is disabled. 57 2535G–AVR–01/07 元器件交易网www.cecb2b.com 8-bit Timer/Counter0 with PWM Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independentOutput Compare Units, and with PWM support. It allows accurate program executiontiming (event management) and wave generation. The main features are:•Two Independent Output Compare Units•Double Buffered Output Compare Registers•Clear Timer on Compare Match (Auto Reload) •Glitch Free, Phase Correct Pulse Width Modulator (PWM)•Variable PWM Period•Frequency Generator •Three Independent Interrupt Sources (TOV0, OCF0A, and OCF0B) A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 26. For theactual placement of I/O pins, refer to “Pinout ATtiny13” on page 2. CPU accessible I/ORegisters, including I/O bits and I/O pins, are shown in bold. The device-specific I/ORegister and bit locations are listed in the “8-bit Timer/Counter Register Description” onpage 69. Figure 26. 8-bit Timer/Counter Block Diagram CountClearDirectionControl LogicclkTnTOVn(Int.Req.)Clock SelectEdgeDetectorTOPBOTTOM( From Prescaler )Timer/CounterTCNTnTnOverview == 0OCnA(Int.Req.)=OCRnAFixedTOPValueWaveformGenerationOCnADATA BUSOCnB(Int.Req.)WaveformGenerationOCnB=OCRnBTCCRnATCCRnBRegisters The Timer/Counter (TCNT0) and Output Compare Registers (OCR0A and OCR0B) are8-bit registers. Interrupt request (abbreviated to Int.Req. in the figure) signals are all vis-ible in the Timer Interrupt Flag Register (TIFR0). All interrupts are individually maskedwith the Timer Interrupt Mask Register (TIMSK0). TIFR0 and TIMSK0 are not shown inthe figure. The Timer/Counter can be clocked internally, via the prescaler, or by an external clocksource on the T0 pin. The Clock Select logic block controls which clock source and edgethe Timer/Counter uses to increment (or decrement) its value. The Timer/Counter isinactive when no clock source is selected. The output from the Clock Select logic isreferred to as the timer clock (clkT0). The double buffered Output Compare Registers (OCR0A and OCR0B) is compared withthe Timer/Counter value at all times. The result of the compare can be used by theWaveform Generator to generate a PWM or variable frequency output on the Output 58 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 Compare pins (OC0A and OC0B). See “Output Compare Unit” on page 60. for details.The Compare Match event will also set the Compare Flag (OCF0A or OCF0B) whichcan be used to generate an Output Compare interrupt request. Definitions Many register and bit references in this section are written in general form. A lower case“n” replaces the Timer/Counter number, in this case 0. A lower case “x” replaces theOutput Compare Unit, in this case Compare Unit A or Compare Unit B. However, whenusing the register or bit defines in a program, the precise form must be used, i.e.,TCNT0 for accessing Timer/Counter0 counter value and so on. The definitions in Table 25 are also used extensively throughout the document.Table 25. DefinitionsBOTTOMMAXTOP The counter reaches the BOTTOM when it becomes 0x00. The counter reaches its MAXimum when it becomes 0xFF (decimal 255).The counter reaches the TOP when it becomes equal to the highestvalue in the count sequence. The TOP value can be assigned to be thefixed value 0xFF (MAX) or the value stored in the OCR0A Register. Theassignment is dependent on the mode of operation. Timer/Counter Clock Sources The Timer/Counter can be clocked by an internal or an external clock source. The clocksource is selected by the Clock Select logic which is controlled by the Clock Select(CS02:0) bits located in the Timer/Counter Control Register (TCCR0B). For details onclock sources and prescaler, see “Timer/Counter Prescaler” on page 75. The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit.Figure 27 shows a block diagram of the counter and its surroundings.Figure 27. Counter Unit Block Diagram DATA BUSTOVn(Int.Req.)Counter Unit Clock SelectcountTCNTncleardirection( From Prescaler )bottomtopControl LogicclkTnEdgeDetectorTnSignal description (internal signals):countdirectionclearclkTntopbottom Increment or decrement TCNT0 by 1.Select between increment and decrement.Clear TCNT0 (set all bits to zero). Timer/Counter clock, referred to as clkT0 in the following.Signalize that TCNT0 has reached maximum value.Signalize that TCNT0 has reached minimum value (zero). 59 2535G–AVR–01/07 元器件交易网www.cecb2b.com Depending of the mode of operation used, the counter is cleared, incremented, or dec-remented at each timer clock (clkT0). clkT0 can be generated from an external or internalclock source, selected by the Clock Select bits (CS02:0). When no clock source isselected (CS02:0 = 0) the timer is stopped. However, the TCNT0 value can be accessedby the CPU, regardless of whether clkT0 is present or not. A CPU write overrides (haspriority over) all counter clear or count operations. The counting sequence is determined by the setting of the WGM01 and WGM00 bitslocated in the Timer/Counter Control Register (TCCR0A) and the WGM02 bit located inthe Timer/Counter Control Register B (TCCR0B). There are close connections betweenhow the counter behaves (counts) and how waveforms are generated on the OutputCompare output OC0A. For more details about advanced counting sequences andwaveform generation, see “Modes of Operation” on page 63. The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operationselected by the WGM01:0 bits. TOV0 can be used for generating a CPU interrupt. Output Compare Unit The 8-bit comparator continuously compares TCNT0 with the Output Compare Regis-ters (OCR0A and OCR0B). Whenever TCNT0 equals OCR0A or OCR0B, thecomparator signals a match. A match will set the Output Compare Flag (OCF0A orOCF0B) at the next timer clock cycle. If the corresponding interrupt is enabled, the Out-put Compare Flag generates an Output Compare interrupt. The Output Compare Flag isautomatically cleared when the interrupt is executed. Alternatively, the flag can becleared by software by writing a logical one to its I/O bit location. The Waveform Gener-ator uses the match signal to generate an output according to operating mode set by theWGM02:0 bits and Compare Output mode (COM0x1:0) bits. The max and bottom sig-nals are used by the Waveform Generator for handling the special cases of the extremevalues in some modes of operation (See “Modes of Operation” on page 63.).Figure 28 shows a block diagram of the Output Compare unit. Figure 28. Output Compare Unit, Block Diagram DATA BUSOCRnxTCNTn= (8-bit Comparator )OCFnx (Int.Req.)topbottomFOCnWaveform GeneratorOCnxWGMn1:0COMnX1:060 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 The OCR0x Registers are double buffered when using any of the Pulse Width Modula-tion (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes ofoperation, the double buffering is disabled. The double buffering synchronizes theupdate of the OCR0x Compare Registers to either top or bottom of the countingsequence. The synchronization prevents the occurrence of odd-length, non-symmetricalPWM pulses, thereby making the output glitch-free. The OCR0x Register access may seem complex, but this is not case. When the doublebuffering is enabled, the CPU has access to the OCR0x Buffer Register, and if doublebuffering is disabled the CPU will access the OCR0x directly. Force Output Compare In non-PWM waveform generation modes, the match output of the comparator can beforced by writing a one to the Force Output Compare (FOC0x) bit. Forcing CompareMatch will not set the OCF0x Flag or reload/clear the timer, but the OC0x pin will beupdated as if a real Compare Match had occurred (the COM0x1:0 bits settings definewhether the OC0x pin is set, cleared or toggled). All CPU write operations to the TCNT0 Register will block any Compare Match thatoccur in the next timer clock cycle, even when the timer is stopped. This feature allowsOCR0x to be initialized to the same value as TCNT0 without triggering an interrupt whenthe Timer/Counter clock is enabled. Since writing TCNT0 in any mode of operation will block all Compare Matches for onetimer clock cycle, there are risks involved when changing TCNT0 when using the OutputCompare Unit, independently of whether the Timer/Counter is running or not. If thevalue written to TCNT0 equals the OCR0x value, the Compare Match will be missed,resulting in incorrect waveform generation. Similarly, do not write the TCNT0 valueequal to BOTTOM when the counter is down-counting. The setup of the OC0x should be performed before setting the Data Direction Registerfor the port pin to output. The easiest way of setting the OC0x value is to use the ForceOutput Compare (FOC0x) strobe bits in Normal mode. The OC0x Registers keep theirvalues even when changing between Waveform Generation modes. Be aware that the COM0x1:0 bits are not double buffered together with the comparevalue. Changing the COM0x1:0 bits will take effect immediately. Compare Match Blocking by TCNT0 Write Using the Output Compare Unit 61 2535G–AVR–01/07 元器件交易网www.cecb2b.com Compare Match Output Unit The Compare Output mode (COM0x1:0) bits have two functions. The Waveform Gener-ator uses the COM0x1:0 bits for defining the Output Compare (OC0x) state at the nextCompare Match. Also, the COM0x1:0 bits control the OC0x pin output source. Figure 29shows a simplified schematic of the logic affected by the COM0x1:0 bit setting. The I/ORegisters, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of thegeneral I/O Port Control Registers (DDR and PORT) that are affected by the COM0x1:0bits are shown. When referring to the OC0x state, the reference is for the internal OC0xRegister, not the OC0x pin. If a system reset occur, the OC0x Register is reset to “0”.Figure 29. Compare Match Output Unit, SchematicCOMnx1COMnx0FOCnWaveformGeneratorDQ1OCnPinOCnxDDATA BUS0QPORTDQDDRclkI/OThe general I/O port function is overridden by the Output Compare (OC0x) from theWaveform Generator if either of the COM0x1:0 bits are set. However, the OC0x pindirection (input or output) is still controlled by the Data Direction Register (DDR) for theport pin. The Data Direction Register bit for the OC0x pin (DDR_OC0x) must be set asoutput before the OC0x value is visible on the pin. The port override function is indepen-dent of the Waveform Generation mode. The design of the Output Compare pin logic allows initialization of the OC0x state beforethe output is enabled. Note that some COM0x1:0 bit settings are reserved for certainmodes of operation. See “8-bit Timer/Counter Register Description” on page 69. Compare Output Mode and Waveform Generation The Waveform Generator uses the COM0x1:0 bits differently in Normal, CTC, and PWMmodes. For all modes, setting the COM0x1:0 = 0 tells the Waveform Generator that noaction on the OC0x Register is to be performed on the next Compare Match. For com-pare output actions in the non-PWM modes refer to Table 26 on page 69. For fast PWMmode, refer to Table 27 on page 69, and for phase correct PWM refer to Table 28 onpage 70. A change of the COM0x1:0 bits state will have effect at the first Compare Match afterthe bits are written. For non-PWM modes, the action can be forced to have immediateeffect by using the FOC0x strobe bits. 62 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Comparepins, is defined by the combination of the Waveform Generation mode (WGM02:0) andCompare Output mode (COM0x1:0) bits. The Compare Output mode bits do not affectthe counting sequence, while the Waveform Generation mode bits do. The COM0x1:0bits control whether the PWM output generated should be inverted or not (inverted ornon-inverted PWM). For non-PWM modes the COM0x1:0 bits control whether the out-put should be set, cleared, or toggled at a Compare Match (See “Compare MatchOutput Unit” on page 62.). For detailed timing information refer to Figure 33, Figure 34, Figure 35 and Figure 36 in“Timer/Counter Timing Diagrams” on page 67. Normal Mode The simplest mode of operation is the Normal mode (WGM02:0 = 0). In this mode thecounting direction is always up (incrementing), and no counter clear is performed. Thecounter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and thenrestarts from the bottom (0x00). In normal operation the Timer/Counter Overflow Flag(TOV0) will be set in the same timer clock cycle as the TCNT0 becomes zero. TheTOV0 Flag in this case behaves like a ninth bit, except that it is only set, not cleared.However, combined with the timer overflow interrupt that automatically clears the TOV0Flag, the timer resolution can be increased by software. There are no special cases toconsider in the Normal mode, a new counter value can be written anytime. The Output Compare Unit can be used to generate interrupts at some given time. Usingthe Output Compare to generate waveforms in Normal mode is not recommended,since this will occupy too much of the CPU time. Clear Timer on Compare Match (CTC) Mode In Clear Timer on Compare or CTC mode (WGM02:0 = 2), the OCR0A Register is usedto manipulate the counter resolution. In CTC mode the counter is cleared to zero whenthe counter value (TCNT0) matches the OCR0A. The OCR0A defines the top value forthe counter, hence also its resolution. This mode allows greater control of the CompareMatch output frequency. It also simplifies the operation of counting external events.The timing diagram for the CTC mode is shown in Figure 30. The counter value(TCNT0) increases until a Compare Match occurs between TCNT0 and OCR0A, andthen counter (TCNT0) is cleared.Figure 30. CTC Mode, Timing Diagram OCnx Interrupt Flag SetTCNTnOCn(Toggle)Period1234(COMnx1:0 = 1)An interrupt can be generated each time the counter value reaches the TOP value byusing the OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can beused for updating the TOP value. However, changing TOP to a value close to BOTTOMwhen the counter is running with none or a low prescaler value must be done with caresince the CTC mode does not have the double buffering feature. If the new value written 63 2535G–AVR–01/07 元器件交易网www.cecb2b.com to OCR0A is lower than the current value of TCNT0, the counter will miss the CompareMatch. The counter will then have to count to its maximum value (0xFF) and wraparound starting at 0x00 before the Compare Match can occur. For generating a waveform output in CTC mode, the OC0A output can be set to toggleits logical level on each Compare Match by setting the Compare Output mode bits totoggle mode (COM0A1:0 = 1). The OC0A value will not be visible on the port pin unlessthe data direction for the pin is set to output. The waveform generated will have a maxi-mum frequency of fOC0 = fclk_I/O/2 when OCR0A is set to zero (0x00). The waveformfrequency is defined by the following equation: fclk_I/O fOCnx=-------------------------------------------------2⋅N⋅(1+OCRnx) The N variable represents the prescale factor (1, 8, , 256, or 1024). As for the Normal mode of operation, the TOV0 Flag is set in the same timer clock cyclethat the counter counts from MAX to 0x00. Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM02:0 = 3 or 7) provides a highfrequency PWM waveform generation option. The fast PWM differs from the other PWMoption by its single-slope operation. The counter counts from BOTTOM to TOP thenrestarts from BOTTOM. TOP is defined as 0xFF when WGM2:0 = 3, and OCR0A whenWGM2:0 = 7. In non-inverting Compare Output mode, the Output Compare (OC0x) iscleared on the Compare Match between TCNT0 and OCR0x, and set at BOTTOM. Ininverting Compare Output mode, the output is set on Compare Match and cleared atBOTTOM. Due to the single-slope operation, the operating frequency of the fast PWMmode can be twice as high as the phase correct PWM mode that use dual-slope opera-tion. This high frequency makes the fast PWM mode well suited for power regulation,rectification, and DAC applications. High frequency allows physically small sized exter-nal components (coils, capacitors), and therefore reduces total system cost. In fast PWM mode, the counter is incremented until the counter value matches the TOPvalue. The counter is then cleared at the following timer clock cycle. The timing diagramfor the fast PWM mode is shown in Figure 31. The TCNT0 value is in the timing diagramshown as a histogram for illustrating the single-slope operation. The diagram includesnon-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0slopes represent Compare Matches between OCR0x and TCNT0. ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 Figure 31. Fast PWM Mode, Timing Diagram OCRnx Interrupt Flag SetOCRnx Update andTOVn Interrupt Flag SetTCNTnOCnOCn(COMnx1:0 = 2)(COMnx1:0 = 3)Period1234567The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches TOP. Ifthe interrupt is enabled, the interrupt handler routine can be used for updating the com-pare value. In fast PWM mode, the compare unit allows generation of PWM waveforms on theOC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM and aninverted PWM output can be generated by setting the COM0x1:0 to three: Setting theCOM0A1:0 bits to one allows the AC0A pin to toggle on Compare Matches if theWGM02 bit is set. This option is not available for the OC0B pin (See Table 27 on page69). The actual OC0x value will only be visible on the port pin if the data direction for theport pin is set as output. The PWM waveform is generated by setting (or clearing) theOC0x Register at the Compare Match between OCR0x and TCNT0, and clearing (orsetting) the OC0x Register at the timer clock cycle the counter is cleared (changes fromTOP to BOTTOM). The PWM frequency for the output can be calculated by the following equation: fclk_I/O fOCnxPWM=-----------------N⋅256 The N variable represents the prescale factor (1, 8, , 256, or 1024). The extreme values for the OCR0A Register represents special cases when generatinga PWM waveform output in the fast PWM mode. If the OCR0A is set equal to BOTTOM,the output will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR0Aequal to MAX will result in a constantly high or low output (depending on the polarity ofthe output set by the COM0A1:0 bits.) A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achievedby setting OC0x to toggle its logical level on each Compare Match (COM0x1:0 = 1). Thewaveform generated will have a maximum frequency of fOC0 = fclk_I/O/2 when OCR0A isset to zero. This feature is similar to the OC0A toggle in CTC mode, except the doublebuffer feature of the Output Compare unit is enabled in the fast PWM mode. 65 2535G–AVR–01/07 元器件交易网www.cecb2b.com Phase Correct PWM Mode The phase correct PWM mode (WGM02:0 = 1 or 5) provides a high resolution phasecorrect PWM waveform generation option. The phase correct PWM mode is based on adual-slope operation. The counter counts repeatedly from BOTTOM to TOP and thenfrom TOP to BOTTOM. TOP is defined as 0xFF when WGM2:0 = 1, and OCR0A whenWGM2:0 = 5. In non-inverting Compare Output mode, the Output Compare (OC0x) iscleared on the Compare Match between TCNT0 and OCR0x while upcounting, and seton the Compare Match while down-counting. In inverting Output Compare mode, theoperation is inverted. The dual-slope operation has lower maximum operation frequencythan single slope operation. However, due to the symmetric feature of the dual-slopePWM modes, these modes are preferred for motor control applications. In phase correct PWM mode the counter is incremented until the counter value matchesTOP. When the counter reaches TOP, it changes the count direction. The TCNT0 valuewill be equal to TOP for one timer clock cycle. The timing diagram for the phase correctPWM mode is shown on Figure 32. The TCNT0 value is in the timing diagram shown asa histogram for illustrating the dual-slope operation. The diagram includes non-invertedand inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes repre-sent Compare Matches between OCR0x and TCNT0.Figure 32. Phase Correct PWM Mode, Timing Diagram OCnx Interrupt Flag SetOCRnx UpdateTOVn Interrupt Flag SetTCNTnOCnOCnPeriod(COMnx1:0 = 2)(COMnx1:0 = 3)123The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOT-TOM. The Interrupt Flag can be used to generate an interrupt each time the counterreaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms onthe OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM. Aninverted PWM output can be generated by setting the COM0x1:0 to three: Setting theCOM0A0 bits to one allows the OC0A pin to toggle on Compare Matches if the WGM02bit is set. This option is not available for the OC0B pin (See Table 28 on page 70). Theactual OC0x value will only be visible on the port pin if the data direction for the port pinis set as output. The PWM waveform is generated by clearing (or setting) the OC0xRegister at the Compare Match between OCR0x and TCNT0 when the counter incre-ments, and setting (or clearing) the OC0x Register at Compare Match between OCR0x 66 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 and TCNT0 when the counter decrements. The PWM frequency for the output whenusing phase correct PWM can be calculated by the following equation: fclk_I/O fOCnxPCPWM=-----------------N⋅510 The N variable represents the prescale factor (1, 8, , 256, or 1024). The extreme values for the OCR0A Register represent special cases when generating aPWM waveform output in the phase correct PWM mode. If the OCR0A is set equal toBOTTOM, the output will be continuously low and if set equal to MAX the output will becontinuously high for non-inverted PWM mode. For inverted PWM the output will havethe opposite logic values. At the very start of period 2 in Figure 32 OCn has a transition from high to low eventhough there is no Compare Match. The point of this transition is to guarantee symmetryaround BOTTOM. There are two cases that give a transition without Compare Match.• OCR0A changes its value from MAX, like in Figure 32. When the OCR0A value is MAX the OCn pin value is the same as the result of a down-counting Compare Match. To ensure symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-counting Compare Match. The timer starts counting from a value higher than the one in OCR0A, and for that reason misses the Compare Match and hence the OCn change that would have happened on the way up. • Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clkT0) is thereforeshown as a clock enable signal in the following figures. The figures include informationon when Interrupt Flags are set. Figure 33 contains timing data for basic Timer/Counteroperation. The figure shows the count sequence close to the MAX value in all modesother than phase correct PWM mode. Figure 33. Timer/Counter Timing Diagram, no Prescaling clkI/OclkTn(clkI/O/1)TCNTnTOVnMAX - 1MAXBOTTOMBOTTOM + 1Figure 34 shows the same timing data, but with the prescaler enabled. 67 2535G–AVR–01/07 元器件交易网www.cecb2b.com Figure 34. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/OclkTn(clkI/O/8)TCNTnTOVnMAX - 1MAXBOTTOMBOTTOM + 1Figure 35 shows the setting of OCF0B in all modes and OCF0A in all modes exceptCTC mode and PWM mode, where OCR0A is TOP. Figure 35. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (fclk_I/O/8) clkI/OclkTn(clkI/O/8)TCNTnOCRnxOCFnxOCRnx - 1OCRnxOCRnx ValueOCRnx + 1OCRnx + 2Figure 36 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fastPWM mode where OCR0A is TOP. Figure 36. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, withPrescaler (fclk_I/O/8) clkI/OclkTn(clkI/O/8)TCNTn(CTC)OCRnxOCFnxTOP - 1TOPTOPBOTTOMBOTTOM + 168 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 8-bit Timer/Counter Register Description Timer/Counter Control Register A – TCCR0A BitRead/WriteInitial Value 7 COM0A1 6 COM0A0 5 COM0B1 4 COM0B0 3 – 2 – 1 WGM01 0 WGM00 TCCR0A R/W0 R/W0 R/W0 R/W0 R0 R0 R/W0 R/W0 •Bits 7:6 – COM01A:0: Compare Match Output A Mode These bits control the Output Compare pin (OC0A) behavior. If one or both of theCOM0A1:0 bits are set, the OC0A output overrides the normal port functionality of theI/O pin it is connected to. However, note that the Data Direction Register (DDR) bit cor-responding to the OC0A pin must be set in order to enable the output driver. When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on theWGM02:0 bit setting. Table 26 shows the COM0A1:0 bit functionality when theWGM02:0 bits are set to a normal or CTC mode (non-PWM).Table 26. Compare Output Mode, non-PWM Mode COM010011 COM000101 Description Normal port operation, OC0A disconnected.Toggle OC0A on Compare MatchClear OC0A on Compare MatchSet OC0A on Compare Match Table 27 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fastPWM mode. Table 27. Compare Output Mode, Fast PWM Mode(1) COM010011Note: COM000101 Description Normal port operation, OC0A disconnected. WGM02 = 0: Normal Port Operation, OC0A Disconnected.WGM02 = 1: Toggle OC0A on Compare Match.Clear OC0A on Compare Match, set OC0A at TOPSet OC0A on Compare Match, clear OC0A at TOP 1.A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Compare Match is ignored, but the set or clear is done at TOP. See “Fast PWMMode” on page for more details. 69 2535G–AVR–01/07 元器件交易网www.cecb2b.com Table 28 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set tophase correct PWM mode. Table 28. Compare Output Mode, Phase Correct PWM Mode(1) COM0A1 0011Note: COM0A0 0101 Description Normal port operation, OC0A disconnected. WGM02 = 0: Normal Port Operation, OC0A Disconnected.WGM02 = 1: Toggle OC0A on Compare Match. Clear OC0A on Compare Match when up-counting. Set OC0A on Compare Match when down-counting. Set OC0A on Compare Match when up-counting. Clear OC0A on Compare Match when down-counting. 1.A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Compare Match is ignored, but the set or clear is done at TOP. See “Phase Cor-rect PWM Mode” on page 66 for more details. •Bits 5:4 – COM0B1:0: Compare Match Output B Mode These bits control the Output Compare pin (OC0B) behavior. If one or both of theCOM0B1:0 bits are set, the OC0B output overrides the normal port functionality of theI/O pin it is connected to. However, note that the Data Direction Register (DDR) bit cor-responding to the OC0B pin must be set in order to enable the output driver. When OC0B is connected to the pin, the function of the COM0B1:0 bits depends on theWGM02:0 bit setting. Table 26 shows the COM0A1:0 bit functionality when theWGM02:0 bits are set to a normal or CTC mode (non-PWM).Table 29. Compare Output Mode, non-PWM Mode COM010011 COM000101 Description Normal port operation, OC0B disconnected.Toggle OC0B on Compare MatchClear OC0B on Compare MatchSet OC0B on Compare Match Table 27 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to fastPWM mode. Table 30. Compare Output Mode, Fast PWM Mode(1) COM010011Note: COM000101 Description Normal port operation, OC0B disconnected.Reserved Clear OC0B on Compare Match, set OC0B at TOPSet OC0B on Compare Match, clear OC0B at TOP 1.A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Compare Match is ignored, but the set or clear is done at TOP. See “Fast PWMMode” on page for more details. 70 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 Table 28 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set tophase correct PWM mode. Table 31. Compare Output Mode, Phase Correct PWM Mode(1) COM0A1 0011Note: COM0A0 0101 Description Normal port operation, OC0B disconnected.Reserved Clear OC0B on Compare Match when up-counting. Set OC0B on Compare Match when down-counting. Set OC0B on Compare Match when up-counting. Clear OC0B on Compare Match when down-counting. 1.A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Compare Match is ignored, but the set or clear is done at TOP. See “Phase Cor-rect PWM Mode” on page 66 for more details. •Bits 3, 2 – Res: Reserved Bits These bits are reserved bits in the ATtiny13 and will always read as zero.•Bits 1:0 – WGM01:0: Waveform Generation Mode Combined with the WGM02 bit found in the TCCR0B Register, these bits control thecounting sequence of the counter, the source for maximum (TOP) counter value, andwhat type of waveform generation to be used, see Table 32. Modes of operation sup-ported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on CompareMatch (CTC) mode, and two types of Pulse Width Modulation (PWM) modes (see“Modes of Operation” on page 63). Table 32. Waveform Generation Mode Bit Description Timer/Counter Mode of OperationNormalPWM, Phase CorrectCTCFast PWMReservedPWM, Phase CorrectReservedFast PWM Update ofOCRx atImmediateTOPImmediateTOP–TOP–TOP TOV FlagSet on(1)(2) MAXBOTTOMMAXMAX–BOTTOM –TOP Mode01234567Notes: WGM200001111 WGM100110011 WGM001010101 TOP0xFF0xFFOCRA0xFF–OCRA–OCRA 1.MAX = 0xFF2.BOTTOM = 0x00 71 2535G–AVR–01/07 元器件交易网www.cecb2b.com Timer/Counter Control Register B – TCCR0B BitRead/WriteInitial Value 7 FOC0A 6 FOC0B 5 – 4 – 3 WGM02 2 CS02 1 CS01 0 CS00 TCCR0B W0 W0 R0 R0 R/W0 R/W0 R/W0 R/W0 •Bit 7 – FOC0A: Force Output Compare A The FOC0A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero whenTCCR0B is written when operating in PWM mode. When writing a logical one to theFOC0A bit, an immediate Compare Match is forced on the Waveform Generation unit.The OC0A output is changed according to its COM0A1:0 bits setting. Note that theFOC0A bit is implemented as a strobe. Therefore it is the value present in theCOM0A1:0 bits that determines the effect of the forced compare. A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC modeusing OCR0A as TOP. The FOC0A bit is always read as zero.•Bit 6 – FOC0B: Force Output Compare B The FOC0B bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero whenTCCR0B is written when operating in PWM mode. When writing a logical one to theFOC0B bit, an immediate Compare Match is forced on the Waveform Generation unit.The OC0B output is changed according to its COM0B1:0 bits setting. Note that theFOC0B bit is implemented as a strobe. Therefore it is the value present in theCOM0B1:0 bits that determines the effect of the forced compare. A FOC0B strobe will not generate any interrupt, nor will it clear the timer in CTC modeusing OCR0B as TOP. The FOC0B bit is always read as zero.•Bits 5:4 – Res: Reserved Bits These bits are reserved bits in the ATtiny13 and will always read as zero.•Bit 3 – WGM02: Waveform Generation Mode See the description in the “Timer/Counter Control Register A – TCCR0A” on page 69.•Bits 2:0 – CS02:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter.Table 33. Clock Select Bit Description CS0200001 CS0100110 CS0001010 Description No clock source (Timer/Counter stopped)clkI/O/(No prescaling)clkI/O/8 (From prescaler)clkI/O/ (From prescaler)clkI/O/256 (From prescaler) 72 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 Table 33. Clock Select Bit Description (Continued) CS0211 CS01011 CS00101 Description clkI/O/1024 (From prescaler) External clock source on T0 pin. Clock on falling edge.External clock source on T0 pin. Clock on rising edge. 1 If external pin modes are used for the Timer/Counter0, transitions on the T0 pin willclock the counter even if the pin is configured as an output. This feature allows softwarecontrol of the counting. Timer/Counter Register – TCNT0 Bit Read/WriteInitialValue 7R/W0 6R/W0 5R/W0 4R/W0 3R/W0 2R/W0 1R/W0 0 TCNT0 R/W0 TCNT0[7:0] The Timer/Counter Register gives direct access, both for read and write operations, tothe Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes)the Compare Match on the following timer clock. Modifying the counter (TCNT0) while the counter is running, introduces a risk of missing a Compare Match between TCNT0and the OCR0x Registers. Output Compare Register A – OCR0A BitRead/WriteInitialValue 7R/W0 6R/W0 5R/W0 4R/W0 3R/W0 2R/W0 1R/W0 0 OCR0A R/W0 OCR0A[7:0] The Output Compare Register A contains an 8-bit value that is continuously comparedwith the counter value (TCNT0). A match can be used to generate an Output Compareinterrupt, or to generate a waveform output on the OC0A pin. Output Compare Register B – OCR0B BitRead/WriteInitialValue 7R/W0 6R/W0 5R/W0 4R/W0 3R/W0 2R/W0 1R/W0 0 OCR0B R/W0 OCR0B[7:0] The Output Compare Register B contains an 8-bit value that is continuously comparedwith the counter value (TCNT0). A match can be used to generate an Output Compareinterrupt, or to generate a waveform output on the OC0B pin. Timer/Counter Interrupt Mask Register – TIMSK0 BitRead/WriteInitialValue 7–R0 6–R0 5–R0 4–R0 3OCIE0BR/W0 2OCIE0AR/W0 1TOIE0R/W0 0–R0 TIMSK0 •Bits 7..4, 0 – Res: Reserved Bits These bits are reserved bits in the ATtiny13 and will always read as zero.•Bit 3 – OCIE0B: Timer/Counter Output Compare Match B Interrupt EnableWhen the OCIE0B bit is written to one, and the I-bit in the Status Register is set, theTimer/Counter Compare Match B interrupt is enabled. The corresponding interrupt is 73 2535G–AVR–01/07 元器件交易网www.cecb2b.com executed if a Compare Match in Timer/Counter occurs, i.e., when the OCF0B bit is set inthe Timer/Counter Interrupt Flag Register – TIFR0. •Bit 2 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt EnableWhen the OCIE0A bit is written to one, and the I-bit in the Status Register is set, theTimer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt isexecuted if a Compare Match in Timer/Counter0 occurs, i.e., when the OCF0A bit is setin the Timer/Counter 0 Interrupt Flag Register – TIFR0.•Bit 1 – TOIE0: Timer/Counter0 Overflow Interrupt Enable When the TOIE0 bit is written to one, and the I-bit in the Status Register is set, theTimer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed ifan overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in theTimer/Counter 0 Interrupt Flag Register – TIFR0. Timer/Counter 0 Interrupt Flag Register – TIFR0 Bit Read/Write InitialValue 7–R0 6–R0 5–R0 4–R0 3OCF0BR/W0 2OCF0AR/W0 1TOV0R/W0 0–R0 TIFR0 •Bits 7..4, 0 – Res: Reserved Bits These bits are reserved bits in the ATtiny13 and will always read as zero.•Bit 3 – OCF0B: Output Compare Flag 0 B The OCF0B bit is set when a Compare Match occurs between the Timer/Counter andthe data in OCR0B – Output Compare Register0 B. OCF0B is cleared by hardwarewhen executing the corresponding interrupt handling vector. Alternatively, OCF0B iscleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0B(Timer/Counter Compare B Match Interrupt Enable), and OCF0B are set, theTimer/Counter Compare Match Interrupt is executed.•Bit 2 – OCF0A: Output Compare Flag 0 A The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 andthe data in OCR0A – Output Compare Register0. OCF0A is cleared by hardware whenexecuting the corresponding interrupt handling vector. Alternatively, OCF0A is clearedby writing a logic one to the flag. When the I-bit in SREG, OCIE0A (Timer/Counter0Compare Match Interrupt Enable), and OCF0A are set, the Timer/Counter0 CompareMatch Interrupt is executed. •Bit 1 – TOV0: Timer/Counter0 Overflow Flag The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared byhardware when executing the corresponding interrupt handling vector. Alternatively,TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0(Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set, the Timer/Counter0Overflow interrupt is executed. The setting of this flag is dependent of the WGM02:0 bit setting. Refer to Table 32,“Waveform Generation Mode Bit Description” on page 71. 74 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 Timer/Counter Prescaler The Timer/Counter can be clocked directly by the system clock (by setting theCSn2:0=1). This provides the fastest operation, with a maximum Timer/Counter clockfrequency equal to system clock frequency (fCLK_I/O). Alternatively, one of four taps fromthe prescaler can be used as a clock source. The prescaled clock has a frequency ofeither fCLK_I/O/8, fCLK_I/O/, fCLK_I/O/256, or fCLK_I/O/1024. The prescaler is free running, i.e., operates independently of the Clock Select logic ofthe Timer/Counter. Since the prescaler is not affected by the Timer/Counter’s clockselect, the state of the prescaler will have implications for situations where a prescaledclock is used. One example of prescaling artifacts occurs when the timer is enabled andclocked by the prescaler (6 > CSn2:0 > 1). The number of system clock cycles fromwhen the timer is enabled to the first count occurs can be from 1 to N+1 system clockcycles, where N equals the prescaler divisor (8, , 256, or 1024). It is possible to use the Prescaler Reset for synchronizing the Timer/Counter to programexecution. External Clock Source An external clock source applied to the T0 pin can be used as Timer/Counter clock(clkT0). The T0 pin is sampled once every system clock cycle by the pin synchronizationlogic. The synchronized (sampled) signal is then passed through the edge detector. Fig-ure 37 shows a functional equivalent block diagram of the T0 synchronization and edgedetector logic. The registers are clocked at the positive edge of the internal system clock(clkI/O). The latch is transparent in the high period of the internal system clock. The edge detector generates one clkT0 pulse for each positive (CSn2:0 = 7) or negative(CSn2:0 = 6) edge it detects.Figure 37. T0 Pin Sampling Tn_sync(To ClockSelect Logic)Prescaler Reset TnDLEQDQDQclkI/OSynchronizationEdge DetectorThe synchronization and edge detector logic introduces a delay of 2.5 to 3.5 systemclock cycles from an edge has been applied to the T0 pin to the counter is updated.Enabling and disabling of the clock input must be done when T0 has been stable for atleast one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulseis generated. Each half period of the external clock applied must be longer than one system clockcycle to ensure correct sampling. The external clock must be guaranteed to have lessthan half the system clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Sincethe edge detector uses sampling, the maximum frequency of an external clock it candetect is half the sampling frequency (Nyquist sampling theorem). However, due to vari-ation of the system clock frequency and duty cycle caused by Oscillator source (crystal,resonator, and capacitors) tolerances, it is recommended that maximum frequency of anexternal clock source is less than fclk_I/O/2.5.An external clock source can not be prescaled. 75 2535G–AVR–01/07 元器件交易网www.cecb2b.com Figure 38. Prescaler for Timer/Counter0 clkI/OClearPSR10T0SynchronizationclkT0Note:1.The synchronization logic on the input pins (T0) is shown in Figure 37. General Timer/Counter Control Register – GTCCR BitRead/WriteInitial Value 7TSMR/W0 6–R0 5–R0 4–R0 3–R0 2–R0 1–R0 0PSR10R/W0 GTCCR •Bit 7 – TSM: Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In thismode, the value that is written to the PSR10 bit is kept, hence keeping the PrescalerReset signal asserted. This ensures that the Timer/Counter is halted and can be config-ured without the risk of advancing during configuration. When the TSM bit is written tozero, the PSR10 bit is cleared by hardware, and the Timer/Counter start counting.•Bit 0 – PSR10: Prescaler Reset Timer/Counter0 When this bit is one, the Timer/Counter0 prescaler will be Reset. This bit is normallycleared immediately by hardware, except if the TSM bit is set. 76 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 Analog Comparator The Analog Comparator compares the input values on the positive pin AIN0 and nega-tive pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage onthe negative pin AIN1, the Analog Comparator output, ACO, is set. The comparator cantrigger a separate interrupt, exclusive to the Analog Comparator. The user can selectInterrupt triggering on comparator output rise, fall or toggle. A block diagram of the com-parator and its surrounding logic is shown in Figure 39.Figure 39. Analog Comparator Block Diagram(2) BANDGAPREFERENCEACBGACMEADENADC MULTIPLEXEROUTPUT(1)Notes: 1.See Table 35 on page 79. 2.Refer to Figure 1 on page 2 and Table 23 on page 52 for Analog Comparator pin placement. ADC Control and Status Register B – ADCSRB BitRead/WriteInitialValue 7–R0 6ACMER/W0 5–R0 4–R0 3–R0 2ADTS2R/W0 1ADTS1R/W0 0ADTS0R/W0 ADCSRB •Bit 6 – ACME: Analog Comparator Multiplexer Enable When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA iszero), the ADC multiplexer selects the negative input to the Analog Comparator. Whenthis bit is written logic zero, AIN1 is applied to the negative input of the Analog Compar-ator. For a detailed description of this bit, see “Analog Comparator Multiplexed Input” onpage 79. Analog Comparator Control and Status Register – ACSR BitRead/WriteInitial Value 7ACDR/W0 6ACBGR/W0 5ACORN/A 4ACIR/W0 3ACIER/W0 2–R0 1ACIS1R/W0 0ACIS0R/W0 ACSR •Bit 7 – ACD: Analog Comparator Disable When this bit is written logic one, the power to the Analog Comparator is switched off.This bit can be set at any time to turn off the Analog Comparator. This will reduce powerconsumption in Active and Idle mode. When changing the ACD bit, the Analog Compar-ator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interruptcan occur when the bit is changed. 77 2535G–AVR–01/07 元器件交易网www.cecb2b.com •Bit 6 – ACBG: Analog Comparator Bandgap Select When this bit is set, a fixed bandgap reference voltage replaces the positive input to theAnalog Comparator. When this bit is cleared, AIN0 is applied to the positive input of theAnalog Comparator. When the bandgap reference is used as input to the Analog Com-parator, it will take certain time for the voltage to stabilize. If not stabilized, the first valuemay give a wrong value. •Bit 5 – ACO: Analog Comparator Output The output of the Analog Comparator is synchronized and then directly connected toACO. The synchronization introduces a delay of 1 - 2 clock cycles. •Bit 4 – ACI: Analog Comparator Interrupt Flag This bit is set by hardware when a comparator output event triggers the interrupt modedefined by ACIS1 and ACIS0. The Analog Comparator interrupt routine is executed ifthe ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hardware when execut-ing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing alogic one to the flag. •Bit 3 – ACIE: Analog Comparator Interrupt Enable When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Ana-log Comparator interrupt is activated. When written logic zero, the interrupt is disabled.•Bit 2 – Res: Reserved Bit This bit is a reserved bit in the ATtiny13 and will always read as zero.•Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select These bits determine which comparator events that trigger the Analog Comparator inter-rupt. The different settings are shown in Table 34.Table 34. ACIS1/ACIS0 Settings ACIS10011 ACIS00101 Interrupt Mode Comparator Interrupt on Output Toggle.Reserved Comparator Interrupt on Falling Output Edge.Comparator Interrupt on Rising Output Edge. When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be dis-abled by clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interruptcan occur when the bits are changed. 78 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 Analog Comparator Multiplexed Input It is possible to select any of the ADC3..0 pins to replace the negative input to the Ana-log Comparator. The ADC multiplexer is used to select this input, and consequently, theADC must be switched off to utilize this feature. If the Analog Comparator MultiplexerEnable bit (ACME in ADCSRB) is set and the ADC is switched off (ADEN in ADCSRA iszero), MUX1..0 in ADMUX select the input pin to replace the negative input to the Ana-log Comparator, as shown in Table 35. If ACME is cleared or ADEN is set, AIN1 isapplied to the negative input to the Analog Comparator.Table 35. Analog Comparator Multiplexed Input ACME01 ADENx10000 MUX1..0xxxx00011011 Analog Comparator Negative InputAIN1AIN1ADC0ADC1ADC2ADC3 1111 Digital Input Disable Register 0 – DIDR0 BitRead/WriteInitialValue 7–R0 6–R0 5ADC0DR/W0 4ADC2DR/W0 3ADC3DR/W0 2ADC1DR/W0 1AIN1DR/W0 0AIN0DR/W0 DIDR0 •Bits 1, 0 – AIN1D, AIN0D: AIN1, AIN0 Digital Input Disable When this bit is written logic one, the digital input buffer on the AIN1/0 pin is disabled.The corresponding PIN Register bit will always read as zero when this bit is set. Whenan analog signal is applied to the AIN1/0 pin and the digital input from this pin is notneeded, this bit should be written logic one to reduce power consumption in the digitalinput buffer. 79 2535G–AVR–01/07 元器件交易网www.cecb2b.com Analog to Digital Converter Features ••••••••••••• 10-bit Resolution 0.5 LSB Integral Non-linearity± 2 LSB Absolute Accuracy13 - 260 µs Conversion Time Up to 15 kSPS at Maximum Resolution Four Multiplexed Single Ended Input ChannelsOptional Left Adjustment for ADC Result Readout0 - VCC ADC Input Voltage Range Selectable 1.1V ADC Reference VoltageFree Running or Single Conversion Mode ADC Start Conversion by Auto Triggering on Interrupt SourcesInterrupt on ADC Conversion CompleteSleep Mode Noise Canceler The ATtiny13 features a 10-bit successive approximation ADC. The ADC is connectedto a 4-channel Analog Multiplexer which allows four single-ended voltage inputs con-structed from the pins of Port B. The single-ended voltage inputs refer to 0V (GND).The ADC contains a Sample and Hold circuit which ensures that the input voltage to theADC is held at a constant level during conversion. A block diagram of the ADC is shownin Figure 40. Internal reference voltages of nominally 1.1V or VCC are provided On-chip. 80 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 Figure 40. Analog to Digital Converter Block Schematic ADC CONVERSIONCOMPLETE IRQINTERRUPTFLAGSADTS[2:0]8-BIT DATA BUSADIFADIE15ADC DATA REGISTER(ADCH/ADCL)ADPS0ADC[9:0]0ADC MULTIPLEXERSELECT (ADMUX)MUX1ADLARREFS1MUX0ADC CTRL. & STATUSREGISTER (ADCSRA)ADATEADPS2ADPS1ADSCADENADIFTRIGGERSELECTMUX DECODERCHANNEL SELECTIONPRESCALERSTARTCONVERSION LOGICVCCINTERNAL 1.1VREFERENCE10-BIT DACSAMPLE & HOLDCOMPARATOR-+ADC3ADC2ADC1ADC0INPUTMUXADC MULTIPLEXEROUTPUTOperation The ADC converts an analog input voltage to a 10-bit digital value through successiveapproximation. The minimum value represents GND and the maximum value representsthe voltage on VCC or an internal 1.1V reference voltage. The analog input channel is selected by writing to the MUX bits in ADMUX. Any of theADC input pins, can be selected as single ended inputs to the ADC. The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltage refer-ence and input channel selections will not go into effect until ADEN is set. The ADCdoes not consume power when ADEN is cleared, so it is recommended to switch off theADC before entering power saving sleep modes. The ADC generates a 10-bit result which is presented in the ADC Data Registers,ADCH and ADCL. By default, the result is presented right adjusted, but can optionallybe presented left adjusted by setting the ADLAR bit in ADMUX. If the result is left adjusted and no more than 8-bit precision is required, it is sufficient toread ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the contentof the data registers belongs to the same conversion. Once ADCL is read, ADC accessto data registers is blocked. This means that if ADCL has been read, and a conversioncompletes before ADCH is read, neither register is updated and the result from the con- 81 2535G–AVR–01/07 元器件交易网www.cecb2b.com version is lost. When ADCH is read, ADC access to the ADCH and ADCL Registers isre-enabled. The ADC has its own interrupt which can be triggered when a conversion completes.When ADC access to the data registers is prohibited between reading of ADCH andADCL, the interrupt will trigger even if the result is lost. Starting a Conversion A single conversion is started by writing a logical one to the ADC Start Conversion bit,ADSC. This bit stays high as long as the conversion is in progress and will be cleared byhardware when the conversion is completed. If a different data channel is selected whilea conversion is in progress, the ADC will finish the current conversion before performingthe channel change. Alternatively, a conversion can be triggered automatically by various sources. Auto Trig-gering is enabled by setting the ADC Auto Trigger Enable bit, ADATE in ADCSRA. Thetrigger source is selected by setting the ADC Trigger Select bits, ADTS in ADCSRB (seedescription of the ADTS bits for a list of the trigger sources). When a positive edgeoccurs on the selected trigger signal, the ADC prescaler is reset and a conversion isstarted. This provides a method of starting conversions at fixed intervals. If the triggersignal still is set when the conversion completes, a new conversion will not be started. Ifanother positive edge occurs on the trigger signal during conversion, the edge will beignored. Note that an Interrupt Flag will be set even if the specific interrupt is disabled orthe Global Interrupt Enable bit in SREG is cleared. A conversion can thus be triggeredwithout causing an interrupt. However, the Interrupt Flag must be cleared in order to trig-ger a new conversion at the next interrupt event. Figure 41. ADC Auto Trigger Logic ADTS[2:0]PRESCALERSTARTADIFSOURCE 1....SOURCE nADSCADATECLKADCCONVERSIONLOGICEDGEDETECTORUsing the ADC Interrupt Flag as a trigger source makes the ADC start a new conversionas soon as the ongoing conversion has finished. The ADC then operates in Free Run-ning mode, constantly sampling and updating the ADC Data Register. The firstconversion must be started by writing a logical one to the ADSC bit in ADCSRA. In thismode the ADC will perform successive conversions independently of whether the ADCInterrupt Flag, ADIF is cleared or not. If Auto Triggering is enabled, single conversions can be started by writing ADSC inADCSRA to one. ADSC can also be used to determine if a conversion is in progress.The ADSC bit will be read as one during a conversion, independently of how the conver-sion was started. 82 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 Prescaling and Conversion Timing Figure 42. ADC Prescaler ADENSTARTCKReset7-BIT ADC PRESCALERADPS0ADPS1ADPS2ADC CLOCK SOURCEBy default, the successive approximation circuitry requires an input clock frequencybetween 50 kHz and 200 kHz to get maximum resolution. If a lower resolution than 10bits is needed, the input clock frequency to the ADC can be higher than 200 kHz to get ahigher sample rate. The ADC module contains a prescaler, which generates an acceptable ADC clock fre-quency from any CPU frequency above 100 kHz. The prescaling is set by the ADPS bitsin ADCSRA. The prescaler starts counting from the moment the ADC is switched on bysetting the ADEN bit in ADCSRA. The prescaler keeps running for as long as the ADENbit is set, and is continuously reset when ADEN is low. When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the con-version starts at the following rising edge of the ADC clock cycle. A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC isswitched on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initializethe analog circuitry. When the bandgap reference voltage is used as input to the ADC, it will take a certaintime for the voltage to stabilize. If not stabilized, the first value read after the first conver-sion may be wrong. The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normalconversion and 14.5 ADC clock cycles after the start of an first conversion. When a con-version is complete, the result is written to the ADC Data Registers, and ADIF is set. InSingle Conversion mode, ADSC is cleared simultaneously. The software may then setADSC again, and a new conversion will be initiated on the first rising ADC clock edge. When Auto Triggering is used, the prescaler is reset when the trigger event occurs. Thisassures a fixed delay from the trigger event to the start of conversion. In this mode, thesample-and-hold takes place two ADC clock cycles after the rising edge on the triggersource signal. Three additional CPU clock cycles are used for synchronization logic.In Free Running mode, a new conversion will be started immediately after the conver-sion completes, while ADSC remains high. For a summary of conversion times, seeTable 36. CK/128CK/16CK/32CK/CK/2CK/4CK/883 2535G–AVR–01/07 元器件交易网www.cecb2b.com Figure 43. ADC Timing Diagram, First Conversion (Single Conversion Mode) First ConversionNextConversionCycle NumberADC ClockADENADSCADIFADCHADCL121213141516171819202122232425123Sign and MSB of ResultLSB of ResultMUX and REFSUpdateSample & HoldConversionCompleteMUX and REFSUpdateFigure 44. ADC Timing Diagram, Single ConversionOne ConversionNext ConversionCycle NumberADC ClockADSCADIFADCHADCL123456710111213123Sign and MSB of ResultLSB of ResultSample & HoldMUX and REFSUpdateConversionCompleteMUX and REFSUpdateFigure 45. ADC Timing Diagram, Auto Triggered Conversion One ConversionNext ConversionCycle NumberADC ClockTriggerSourceADATEADIFADCHADCL12345671011121312Sign and MSB of ResultLSB of ResultSample &HoldMUX and REFS UpdateConversionCompletePrescalerResetPrescaler Reset84 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 Figure 46. ADC Timing Diagram, Free Running Conversion One Conversion111213Next Conversion1234Cycle NumberADC ClockADSCADIFADCHADCLSign and MSB of ResultLSB of ResultSample & HoldMUX and REFSUpdateConversionCompleteTable 36. ADC Conversion Time ConditionFirst conversionNormal conversionsAuto Triggered conversions Sample & Hold (Cycles from Start of Conversion) 13.51.52 Conversion Time (Cycles) 251313.5 85 2535G–AVR–01/07 元器件交易网www.cecb2b.com Changing Channel or Reference Selection The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a tem-porary register to which the CPU has random access. This ensures that the channelsand reference selection only takes place at a safe point during the conversion. Thechannel and reference selection is continuously updated until a conversion is started.Once the conversion starts, the channel and reference selection is locked to ensure asufficient sampling time for the ADC. Continuous updating resumes in the last ADCclock cycle before the conversion completes (ADIF in ADCSRA is set). Note that theconversion starts on the following rising ADC clock edge after ADSC is written. The useris thus advised not to write new channel or reference selection values to ADMUX untilone ADC clock cycle after ADSC is written. If Auto Triggering is used, the exact time of the triggering event can be indeterministic.Special care must be taken when updating the ADMUX Register, in order to controlwhich conversion will be affected by the new settings. If both ADATE and ADEN is written to one, an interrupt event can occur at any time. Ifthe ADMUX Register is changed in this period, the user cannot tell if the next conversionis based on the old or the new settings. ADMUX can be safely updated in the followingways: 1.When ADATE or ADEN is cleared. 2.During conversion, minimum one ADC clock cycle after the trigger event.3.After a conversion, before the Interrupt Flag used as trigger source is cleared.When updating ADMUX in one of these conditions, the new settings will affect the nextADC conversion. ADC Input Channels When changing channel selections, the user should observe the following guidelines toensure that the correct channel is selected: In Single Conversion mode, always select the channel before starting the conversion.The channel selection may be changed one ADC clock cycle after writing one to ADSC.However, the simplest method is to wait for the conversion to complete before changingthe channel selection. In Free Running mode, always select the channel before starting the first conversion.The channel selection may be changed one ADC clock cycle after writing one to ADSC.However, the simplest method is to wait for the first conversion to complete, and thenchange the channel selection. Since the next conversion has already started automati-cally, the next result will reflect the previous channel selection. Subsequent conversionswill reflect the new channel selection. 86 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 ADC Voltage Reference The reference voltage for the ADC (VREF) indicates the conversion range for the ADC.Single ended channels that exceed VREF will result in codes close to 0x3FF. VREF can beselected as either VCC, or internal 1.1V reference, or external AREF pin. The first ADCconversion result after switching reference voltage source may be inaccurate, and theuser is advised to discard this result. The ADC features a noise canceler that enables conversion during sleep mode toreduce noise induced from the CPU core and other I/O peripherals. The noise cancelercan be used with ADC Noise Reduction and Idle mode. To make use of this feature, thefollowing procedure should be used: 1.Make sure that the ADC is enabled and is not busy converting. Single Con-version mode must be selected and the ADC conversion complete interruptmust be enabled.2.Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a con-version once the CPU has been halted.3.If no other interrupts occur before the ADC conversion completes, the ADC interrupt will wake up the CPU and execute the ADC Conversion Completeinterrupt routine. If another interrupt wakes up the CPU before the ADC con-version is complete, that interrupt will be executed, and an ADC ConversionComplete interrupt request will be generated when the ADC conversioncompletes. The CPU will remain in active mode until a new sleep commandis executed.Note that the ADC will not be automatically turned off when entering other sleep modesthan Idle mode and ADC Noise Reduction mode. The user is advised to write zero toADEN before entering such sleep modes to avoid excessive power consumption. ADC Noise Canceler 87 2535G–AVR–01/07 元器件交易网www.cecb2b.com Analog Input Circuitry The analog input circuitry for single ended channels is illustrated in Figure 47. An analogsource applied to ADCn is subjected to the pin capacitance and input leakage of thatpin, regardless of whether that channel is selected as input for the ADC. When the chan-nel is selected, the source must drive the S/H capacitor through the series resistance(combined resistance in the input path). The ADC is optimized for analog signals with an output impedance of approximately10kΩ or less. If such a source is used, the sampling time will be negligible. If a sourcewith higher impedance is used, the sampling time will depend on how long time thesource needs to charge the S/H capacitor, with can vary widely. The user is recom-mended to only use low impedant sources with slowly varying signals, since thisminimizes the required charge transfer to the S/H capacitor. Signal components higher than the Nyquist frequency (fADC/2) should not be present toavoid distortion from unpredictable signal convolution. The user is advised to removehigh frequency components with a low-pass filter before applying the signals as inputsto the ADC. Figure 47. Analog Input Circuitry IIHADCn1..100 kΩCS/H= 14 pFIILVCC/288 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 Analog Noise Canceling Techniques Digital circuitry inside and outside the device generates EMI which might affect theaccuracy of analog measurements. If conversion accuracy is critical, the noise level canbe reduced by applying the following techniques: 1.Keep analog signal paths as short as possible. Make sure analog tracks run over the analog ground plane, and keep them well away from high-speedswitching digital tracks.2.Use the ADC noise canceler function to reduce induced noise from the CPU.3.If any port pins are used as digital outputs, it is essential that these do not switch while a conversion is in progress. ADC Accuracy Definitions An n-bit single-ended ADC converts a voltage linearly between GND and VREF in 2nsteps (LSBs). The lowest code is read as 0, and the highest code is read as 2n-1. Several parameters describe the deviation from the ideal behavior:• Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5 LSB). Ideal value: 0 LSB. Figure 48. Offset Error Output CodeIdeal ADCActual ADCOffsetErrorVREFInput Voltage• Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB 2535G–AVR–01/07 元器件交易网www.cecb2b.com Figure 49. Gain Error Output CodeGainErrorIdeal ADCActual ADCVREFInput Voltage• Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0 LSB. Figure 50. Integral Non-linearity (INL) Output CodeINLIdeal ADCActual ADCVREFInput Voltage• Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB. 90 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 Figure 51. Differential Non-linearity (DNL) Output Code0x3FF1 LSBDNL0x0000VREFInput Voltage• Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 LSB wide) will code to the same value. Always ± 0.5 LSB. Absolute Accuracy: The maximum deviation of an actual (unadjusted) transition compared to an ideal transition for any code. This is the compound effect of offset, gain error, differential error, non-linearity, and quantization error. Ideal value: ± 0.5 LSB. • ADC Conversion Result After the conversion is complete (ADIF is high), the conversion result can be found inthe ADC Result Registers (ADCL, ADCH). For single ended conversion, the result is V⋅1024 ADC=----IN----------------------VREF where VIN is the voltage on the selected input pin and VREF the selected voltage refer-ence (see Table 37 on page 92 and Table 38 on page 92). 0x000 represents analog ground, and 0x3FF represents the selected reference voltage minus one LSB. ADC Multiplexer Selection Register – ADMUX BitRead/WriteInitialValue 7–R0 6REFS0R/W0 5ADLARR/W0 4–R0 3–R0 2–R0 1MUX1R/W0 0MUX0R/W0 ADMUX •Bit 7 – Res: Reserved Bit This bit is reserved bit in the ATtiny13 and will always read as zero.•Bit 6 – REFS0: Reference Selection Bit 91 2535G–AVR–01/07 元器件交易网www.cecb2b.com This bit selects the voltage reference for the ADC, as shown in Table 37. If this bit ischanged during a conversion, the change will not go in effect until this conversion iscomplete (ADIF in ADCSRA is set). Table 37. Voltage Reference Selections for ADC REFS001 Voltage Reference SelectionVCC used as analog reference.Internal Voltage Reference. • Bit 5 – ADLAR: ADC Left Adjust Result The ADLAR bit affects the presentation of the ADC conversion result in the ADC DataRegister. Write one to ADLAR to left adjust the result. Otherwise, the result is rightadjusted. Changing the ADLAR bit will affect the ADC Data Register immediately,regardless of any ongoing conversions. For a complete description of this bit, see “TheADC Data Register – ADCL and ADCH” on page 93.•Bits 4:2 – Res: Reserved Bits These bits are reserved bits in the ATtiny13 and will always read as zero.•Bits 1:0 – MUX1:0: Analog Channel Selection Bits The value of these bits selects which combination of analog inputs are connected to theADC. See Table 38 for details. If these bits are changed during a conversion, thechange will not go in effect until this conversion is complete (ADIF in ADCSRA is set).Table 38. Input Channel Selections MUX1..000011011 Single Ended InputADC0 (PB5)ADC1 (PB2)ADC2 (PB4)ADC3 (PB3) ADC Control and Status Register A – ADCSRA BitRead/WriteInitial Value 7ADENR/W0 6ADSCR/W0 5ADATER/W0 4ADIFR/W0 3ADIER/W0 2ADPS2R/W0 1ADPS1R/W0 0ADPS0R/W0 ADCSRA •Bit 7 – ADEN: ADC Enable Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turn-ing the ADC off while a conversion is in progress, will terminate this conversion.•Bit 6 – ADSC: ADC Start Conversion In Single Conversion mode, write this bit to one to start each conversion. In Free Run-ning mode, write this bit to one to start the first conversion. The first conversion afterADSC has been written after the ADC has been enabled, or if ADSC is written at thesame time as the ADC is enabled, will take 25 ADC clock cycles instead of the normal13. This first conversion performs initialization of the ADC. ADSC will read as one as long as a conversion is in progress. When the conversion iscomplete, it returns to zero. Writing zero to this bit has no effect.•Bit 5 – ADATE: ADC Auto Trigger Enable 92 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start a conversion on a positive edge of the selected trigger signal. The trigger source isselected by setting the ADC Trigger Select bits, ADTS in ADCSRB.•Bit 4 – ADIF: ADC Interrupt Flag This bit is set when an ADC conversion completes and the data registers are updated.The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit inSREG are set. ADIF is cleared by hardware when executing the corresponding interrupthandling vector. Alternatively, ADIF is cleared by writing a logical one to the flag.Beware that if doing a Read-Modify-Write on ADCSRA, a pending interrupt can be dis-abled. This also applies if the SBI and CBI instructions are used.•Bit 3 – ADIE: ADC Interrupt Enable When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Com-plete Interrupt is activated. •Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits These bits determine the division factor between the system clock frequency and theinput clock to the ADC. Table 39. ADC Prescaler Selections ADPS200001111 ADPS100110011 ADPS001010101 Division Factor 22481632128 The ADC Data Register – ADCL and ADCHADLAR = 0 Bit 15–ADC77 Read/WriteInitialValue RR00 14–ADC66RR00 13–ADC55RR00 12–ADC44RR00 11–ADC33RR00 10–ADC22RR00 9ADC9ADC11RR00 8ADC8ADC00RR00 ADCHADCL ADLAR = 1 Bit 15ADC9ADC17 Read/Write RR 14ADC8ADC06RR 13ADC7–5RR 12ADC6–4RR 11ADC5–3RR 10ADC4–2RR 9ADC3–1RR 8ADC2–0RR ADCHADCL 93 2535G–AVR–01/07 元器件交易网www.cecb2b.com InitialValue00 00 00 00 00 00 00 00 When an ADC conversion is complete, the result is found in these two registers.When ADCL is read, the ADC Data Register is not updated until ADCH is read. Conse-quently, if the result is left adjusted and no more than 8-bit precision is required, it issufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result isread from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared(default), the result is right adjusted. •ADC9:0: ADC Conversion Result These bits represent the result from the conversion, as detailed in “ADC ConversionResult” on page 91. ADC Control and Status Register B – ADCSRB BitRead/WriteInitial Value 7–R0 6ACMER/W0 5–R0 4–R0 3–R0 2ADTS2R/W0 1ADTS1R/W0 0ADTS0R/W0 ADCSRB •Bits 7, 5..3 – Res: Reserved Bits These bits are reserved bits in the ATtiny13 and will always read as zero.•Bits 2:0 – ADTS2:0: ADC Auto Trigger Source If ADATE in ADCSRA is written to one, the value of these bits selects which source willtrigger an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have noeffect. A conversion will be triggered by the rising edge of the selected Interrupt Flag.Note that switching from a trigger source that is cleared to a trigger source that is set,will generate a positive edge on the trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running mode (ADTS[2:0]=0) will not cause a trig-ger event, even if the ADC Interrupt Flag is set.Table 40. ADC Auto Trigger Source Selections ADTS20000111 ADTS10011001 ADTS00101010 Trigger SourceFree Running modeAnalog ComparatorExternal Interrupt Request 0Timer/Counter Compare Match ATimer/Counter Overflow Timer/Counter Compare Match BPin Change Interrupt Request Digital Input Disable Register 0 – DIDR0 BitRead/WriteInitialValue 7–R0 6–R0 5ADC0DR/W0 4ADC2DR/W0 3ADC3DR/W0 2ADC1DR/W0 1AIN1DR/W0 0AIN0DR/W0 DIDR0 •Bits 5..2 – ADC3D..ADC0D: ADC3..0 Digital Input Disable 94 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 When this bit is written logic one, the digital input buffer on the corresponding ADC pin isdisabled. The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC3..0 pin and the digital input from this pin isnot needed, this bit should be written logic one to reduce power consumption in the dig-ital input buffer. 2535G–AVR–01/07 95 元器件交易网www.cecb2b.com debugWIRE On-chip Debug System Features •••••••••• Complete Program Flow Control Emulates All On-chip Functions, Both Digital and Analog, except RESET PinReal-time Operation Symbolic Debugging Support (Both at C and Assembler Source Level, or for Other HLLs)Unlimited Number of Program Break Points (Using Software Break Points)Non-intrusive Operation Electrical Characteristics Identical to Real DeviceAutomatic Configuration SystemHigh-Speed Operation Programming of Non-volatile Memories Overview The debugWIRE On-chip debug system uses a One-wire, bi-directional interface to con-trol the program flow, execute AVR instructions in the CPU and to program the differentnon-volatile memories. When the debugWIRE Enable (DWEN) Fuse is programmed and Lock bits are unpro-grammed, the debugWIRE system within the target device is activated. The RESET portpin is configured as a wire-AND (open-drain) bi-directional I/O pin with pull-up enabledand becomes the communication gateway between target and emulator. Figure 52. The debugWIRE Setup Physical Interface 1.8 - 5.5VVCCdWdW(RESET)GNDFigure 52 shows the schematic of a target MCU, with debugWIRE enabled, and theemulator connector. The system clock is not affected by debugWIRE and will always bethe clock source selected by the CKSEL Fuses. When designing a system where debugWIRE will be used, the following observationsmust be made for correct operation:•• Pull-Up resistor on the dW/(RESET) line must be in the range of 10k to 20 kΩ. However, the pull-up resistor is optional. Connecting the RESET pin directly to VCC will not work. 96 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 •• Capacitors inserted on the RESET pin must be disconnected when using debugWire. All external reset sources must be disconnected. Software Break Points ting a Break Point in AVR Studio® will insert a BREAK instruction in the Program debugWIRE supports Program memory Break Points by the AVR Break instruction. Set-memory. The instruction replaced by the BREAK instruction will be stored. When pro-gram execution is continued, the stored instruction will be executed before continuingfrom the Program memory. A break can be inserted manually by putting the BREAKinstruction in the program. The Flash must be re-programmed each time a Break Point is changed. This is auto-matically handled by AVR Studio through the debugWIRE interface. The use of BreakPoints will therefore reduce the Flash Data retention. Devices used for debugging pur-poses should not be shipped to end customers. Limitations of debugWIRE The debugWIRE communication pin (dW) is physically located on the same pin asExternal Reset (RESET). An External Reset source is therefore not supported when thedebugWIRE is enabled. The debugWIRE system accurately emulates all I/O functions when running at fullspeed, i.e., when the program in the CPU is running. When the CPU is stopped, caremust be taken while accessing some of the I/O Registers via the debugger (AVR Stu-dio). See the debugWIRE documentation for detailed description of the limitations.A programmed DWEN Fuse enables some parts of the clock system to be running in allsleep modes. This will increase the power consumption while in sleep. Thus, the DWENFuse should be disabled when debugWire is not used. debugWIRE Related Register in I/O Memory debugWire Data Register – DWDR The following section describes the registers used with the debugWire. BitRead/WriteInitialValue 7R/W0 6R/W0 5R/W0 4R/W0 3R/W0 2R/W0 1R/W0 0 DWDR R/W0 DWDR[7:0] The DWDR Register provides a communication channel from the running program inthe MCU to the debugger. This register is only accessible by the debugWIRE and cantherefore not be used as a general purpose register in the normal operations. 97 2535G–AVR–01/07 元器件交易网www.cecb2b.com Self-Programming the Flash The device provides a Self-Programming mechanism for downloading and uploadingprogram code by the MCU itself. The Self-Programming can use any available datainterface and associated protocol to read code and write (program) that code into theProgram memory. The Program memory is updated in a page by page fashion. Before programming apage with the data stored in the temporary page buffer, the page must be erased. Thetemporary page buffer is filled one word at a time using SPM and the buffer can be filledeither before the Page Erase command or between a Page Erase and a Page Writeoperation: Alternative 1, fill the buffer before a Page Erase•••••• Fill temporary page bufferPerform a Page ErasePerform a Page WritePerform a Page EraseFill temporary page bufferPerform a Page Write Alternative 2, fill the buffer after Page Erase If only a part of the page needs to be changed, the rest of the page must be stored (forexample in the temporary page buffer) before the erase, and then be re-written. Whenusing alternative 1, the Boot Loader provides an effective Read-Modify-Write featurewhich allows the user software to first read the page, do the necessary changes, andthen write back the modified data. If alternative 2 is used, it is not possible to read theold data while loading since the page is already erased. The temporary page buffer canbe accessed in a random sequence. It is essential that the page address used in boththe Page Erase and Page Write operation is addressing the same page. Performing Page Erase by SPM To execute Page Erase, set up the address in the Z-pointer, write “00000011” toSPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data inR1 and R0 is ignored. The page address must be written to PCPAGE in the Z-register.Other bits in the Z-pointer will be ignored during this operation.• Filling the Temporary Buffer (Page Loading) The CPU is halted during the Page Erase operation. To write an instruction word, set up the address in the Z-pointer and data in R1:R0, write“00000001” to SPMCSR and execute SPM within four clock cycles after writingSPMCSR. The content of PCWORD in the Z-register is used to address the data in thetemporary buffer. The temporary buffer will auto-erase after a Page Write operation orby writing the CTPB bit in SPMCSR. It is also erased after a system reset. Note that it isnot possible to write more than one time to each address without erasing the temporarybuffer. If the EEPROM is written in the middle of an SPM Page Load operation, all data loadedwill be lost. Performing a Page Write To execute Page Write, set up the address in the Z-pointer, write “00000101” toSPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data inR1 and R0 is ignored. The page address must be written to PCPAGE. Other bits in theZ-pointer must be written to zero during this operation.• The CPU is halted during the Page Write operation. 98 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 Addressing the Flash During Self-Programming The Z-pointer is used to address the SPM commands. BitZH (R31)ZL(R30) 15Z15Z77 14Z14Z66 13Z13Z55 12Z12Z44 11Z11Z33 10Z10Z22 9Z9Z11 8Z8Z00 Since the Flash is organized in pages (see Table 46 on page 106), the Program Countercan be treated as having two different sections. One section, consisting of the least sig-nificant bits, is addressing the words within a page, while the most significant bits areaddressing the pages. This is shown in Figure 53. Note that the Page Erase and PageWrite operations are addressed independently. Therefore it is of major importance thatthe software addresses the same page in both the Page Erase and Page Writeoperation. The LPM instruction uses the Z-pointer to store the address. Since this instructionaddresses the Flash byte-by-byte, also the LSB (bit Z0) of the Z-pointer is used.Figure 53. Addressing the Flash During SPM(1) BITZ - REGISTERPCMSBPCPAGE15ZPCMSBZPAGEMSB100PROGRAMCOUNTERPAGEMSBPCWORDPAGE ADDRESSWITHIN THE FLASHPROGRAM MEMORYPAGEWORD ADDRESSWITHIN A PAGEPAGEINSTRUCTION WORDPCWORD[PAGEMSB:0]:000102 PAGEENDNote:1.The different variables used in Figure 53 are listed in Table 46 on page 106. 99 2535G–AVR–01/07 元器件交易网www.cecb2b.com Store Program Memory Control and Status Register – SPMCSR The Store Program Memory Control and Status Register contains the control bitsneeded to control the Program memory operations. BitRead/WriteInitialValue 7 – 6 – 5 – 4 CTPB 3 RFLB 2 PGWRT 1 PGERS 0 SELFPRGEN SPMCSR R0 R0 R0 R/W0 R/W0 R/W0 R/W0 R/W0 •Bits 7..5 – Res: Reserved Bits These bits are reserved bits in the ATtiny13 and always read as zero.•Bit 4 – CTPB: Clear Temporary Page Buffer If the CTPB bit is written while filling the temporary page buffer, the temporary pagebuffer will be cleared and the data will be lost.•Bit 3 – RFLB: Read Fuse and Lock Bits An LPM instruction within three cycles after RFLB and SELFPRGEN are set in theSPMCSR Register, will read either the Lock bits or the Fuse bits (depending on Z0 inthe Z-pointer) into the destination register. See “EEPROM Write Prevents Writing toSPMCSR” on page 101 for details.•Bit 2 – PGWRT: Page Write If this bit is written to one at the same time as SELFPRGEN, the next SPM instructionwithin four clock cycles executes Page Write, with the data stored in the temporarybuffer. The page address is taken from the high part of the Z-pointer. The data in R1 andR0 are ignored. The PGWRT bit will auto-clear upon completion of a Page Write, or if noSPM instruction is executed within four clock cycles. The CPU is halted during the entire Page Write operation. •Bit 1 – PGERS: Page Erase If this bit is written to one at the same time as SELFPRGEN, the next SPM instructionwithin four clock cycles executes Page Erase. The page address is taken from the highpart of the Z-pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clearupon completion of a Page Erase, or if no SPM instruction is executed within four clockcycles. The CPU is halted during the entire Page Write operation.•Bit 0 – SELFPRGEN: Self Programming Enable This bit enables the SPM instruction for the next four clock cycles. If written to onetogether with either CTPB, RFLB, PGWRT, or PGERS, the following SPM instructionwill have a special meaning, see description above. If only SELFPRGEN is written, thefollowing SPM instruction will store the value in R1:R0 in the temporary page bufferaddressed by the Z-pointer. The LSB of the Z-pointer is ignored. The SELFPRGEN bitwill auto-clear upon completion of an SPM instruction, or if no SPM instruction is exe-cuted within four clock cycles. During Page Erase and Page Write, the SELFPRGEN bitremains high until the operation is completed. Writing any other combination than “10001”, “01001”, “00101”, “00011” or “00001” in thelower five bits will have no effect. 100 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 EEPROM Write Prevents Writing to SPMCSR Note that an EEPROM write operation will block all software programming to Flash.Reading the Fuses and Lock bits from software will also be prevented during theEEPROM write operation. It is recommended that the user checks the status bit (EEPE)in the EECR Register and verifies that the bit is cleared before writing to the SPMCSRRegister. It is possible to read both the Fuse and Lock bits from software. To read the Lock bits,load the Z-pointer with 0x0001 and set the RFLB and SELFPRGEN bits in SPMCSR.When an LPM instruction is executed within three CPU cycles after the RFLB andSELFPRGEN bits are set in SPMCSR, the value of the Lock bits will be loaded in thedestination register. The RFLB and SELFPRGEN bits will auto-clear upon completion ofreading the Lock bits or if no LPM instruction is executed within three CPU cycles or noSPM instruction is executed within four CPU cycles. When RFLB and SELFPRGEN arecleared, LPM will work as described in the Instruction set Manual. BitRd 7– 6– 5– 4– 3– 2– 1LB2 0LB1 Reading the Fuse and Lock Bits from Software The algorithm for reading the Fuse Low byte is similar to the one described above forreading the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 andset the RFLB and SELFPRGEN bits in SPMCSR. When an LPM instruction is executedwithin three cycles after the RFLB and SELFPRGEN bits are set in the SPMCSR, thevalue of the Fuse Low byte (FLB) will be loaded in the destination register as shownbelow. Refer to Table 45 on page 104 for a detailed description and mapping of theFuse Low byte. BitRd 7FLB7 6FLB6 5FLB5 4FLB4 3FLB3 2FLB2 1FLB1 0FLB0 Similarly, when reading the Fuse High byte, load 0x0003 in the Z-pointer. When an LPMinstruction is executed within three cycles after the RFLB and SELFPRGEN bits are setin the SPMCSR, the value of the Fuse High byte (FHB) will be loaded in the destinationregister as shown below. Refer to Table 44 on page 104 for detailed description andmapping of the Fuse High byte. BitRd 7FHB7 6FHB6 5FHB5 4FHB4 3FHB3 2FHB2 1FHB1 0FHB0 Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits thatare unprogrammed, will be read as one. 101 2535G–AVR–01/07 元器件交易网www.cecb2b.com Preventing Flash Corruption During periods of low VCC, the Flash program can be corrupted because the supply volt-age is too low for the CPU and the Flash to operate properly. These issues are the sameas for board level systems using the Flash, and the same design solutions should beapplied. A Flash program corruption can be caused by two situations when the voltage is too low.First, a regular write sequence to the Flash requires a minimum voltage to operate cor-rectly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltagefor executing instructions is too low. Flash corruption can easily be avoided by following these design recommendations (oneis sufficient): 1.Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD) ifthe operating voltage matches the detection level. If not, an external low VCCreset protection circuit can be used. If a reset occurs while a write operation is inprogress, the write operation will be completed provided that the power supplyvoltage is sufficient.2.Keep the AVR core in Power-down sleep mode during periods of low VCC. This will prevent the CPU from attempting to decode and execute instructions, effec-tively protecting the SPMCSR Register and thus the Flash from unintentionalwrites. Programming Time for Flash when Using SPMThe calibrated RC Oscillator is used to time Flash accesses. Table 41 shows the typicalprogramming time for Flash accesses from the CPU.Table 41. SPM Programming Time Symbol Flash write (Page Erase, Page Write, and write Lock bits by SPM) Min Programming Time 3.7 ms Max Programming Time 4.5 ms 102 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 Memory Programming Program And Data Memory Lock Bits This section describes the different methods for Programming the ATtiny13 memories. The ATtiny13 provides two Lock bits which can be left unprogrammed (“1”) or can beprogrammed (“0”) to obtain the additional security listed in Table 43. The Lock bits canonly be erased to “1” with the Chip Erase command. Program memory can be read out via the debugWIRE interface when the DWEN fuse isprogrammed, even if the Lock Bits are set. Thus, when Lock Bit security is required,should always debugWIRE be disabled by clearing the DWEN fuse. Table 42. Lock Bit Byte(1) Lock Bit Byte Bit No7632 LB2LB1Note: 10 Description––––––Lock bitLock bit Default Value1 (unprogrammed)1 (unprogrammed)1 (unprogrammed)1 (unprogrammed)1 (unprogrammed)1 (unprogrammed)1 (unprogrammed)1 (unprogrammed) 1.“1” means unprogrammed, “0” means programmed Table 43. Lock Bit Protection Modes(1)(2) Memory Lock BitsLB Mode 1 LB21 LB11 No memory lock features enabled. Further programming of the Flash and EEPROM is disabled in High-voltage and Serial Programming mode. The Fuse bits are locked in both Serial and High-voltage Programming mode.(1) debugWire is disabled. Further programming and verification of the Flash and EEPROM is disabled in High-voltage and Serial Programming mode. The Fuse bits are locked in both Serial and High-voltage Programming mode.(1) debugWire is disabled.Protection Type 210 300 Notes: 1.Program the Fuse bits before programming the LB1 and LB2.2.“1” means unprogrammed, “0” means programmed 103 2535G–AVR–01/07 元器件交易网www.cecb2b.com Fuse Bytes The ATtiny13 has two Fuse bytes. Table 44 and Table 45 describe briefly the functional-ity of all the fuses and how they are mapped into the Fuse bytes. Note that the fuses areread as logical zero, “0”, if they are programmed.Table 44. Fuse High Byte Fuse High Byte––– SELFPRGENDWEN(3) BODLEVEL1(1)BODLEVEL0(1)RSTDISBL(4)Notes: Bit No763210 Description––– Self Programming EnabledebugWire Enable Brown-out Detector trigger levelBrown-out Detector trigger levelExternal Reset disable Default Value1 (unprogrammed)1 (unprogrammed)1 (unprogrammed)1 (unprogrammed)1 (unprogrammed)1 (unprogrammed)1 (unprogrammed)1 (unprogrammed) 1.See Table 13 on page 33 for BODLEVEL Fuse decoding. 2.See “Alternate Functions of Port B” on page 51 for description of RSTDISBL and DWEN Fuses. 3.DWEN must be unprogrammed when Lock Bit security is required. See “Program And Data Memory Lock Bits” on page 103. 4.When programming the RSTDISBL Fuse, High-voltage Serial programming has to be used to change fuses to perform further programming. Table 45. Fuse Low Byte Fuse Low ByteSPIEN(1) Bit No7 Description Enable Serial Program and Data DownloadingEEPROM memory is preserved through the Chip Erase Watchdog Timer always on Divide clock by 8Select start-up timeSelect start-up timeSelect Clock sourceSelect Clock source Default Value 0 (programmed, SPI prog. enabled) 1 (unprogrammed, EEPROM not preserved) EESAVE6 WDTON(2)CKDIV8(5)SUT1SUT0CKSEL1CKSEL0Notes: 3210 1 (unprogrammed)0 (programmed)1 (unprogrammed)(3)0 (programmed)(3)1 (unprogrammed)(4)0 (programmed)(4) 1.The SPIEN Fuse is not accessible in SPI Programming mode. 2.See “Watchdog Timer Control Register - WDTCR” on page 39 for details. Program-ming this fues will disable the Watchdog Timer Interrupt. 3.The default value of SUT1..0 results in maximum start-up time for the default clock source. See Table 5 on page 23 for details. 4.The default setting of CKSEL1..0 results in internal RC Oscillator @ 9.6 MHz. See Table 4 on page 23 for details. 5.See “System Clock Prescaler” on page 25 for details. 104 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 The status of the Fuse bits is not affected by Chip Erase. Note that the Fuse bits arelocked if Lock bit1 (LB1) is programmed. Program the Fuse bits before programming theLock bits. 2535G–AVR–01/07 105 元器件交易网www.cecb2b.com Latching of Fuses The fuse values are latched when the device enters programming mode and changes ofthe fuse values will have no effect until the part leaves Programming mode. This doesnot apply to the EESAVE Fuse which will take effect once it is programmed. The fusesare also latched on Power-up in Normal mode. All Atmel microcontrollers have a three-byte signature code which identifies the device.This code can be read in both serial and High-voltage Programming mode, also whenthe device is locked. The three bytes reside in a separate address space.For the ATtiny13 the signature bytes are: 1.0x000: 0x1E (indicates manufactured by Atmel).2.0x001: 0x90 (indicates 1 KB Flash memory). 3.0x002: 0x07 (indicates ATtiny13 device when 0x001 is 0x90). Signature Bytes Calibration Byte Signature area of the ATtiny13 has one byte of calibration data for the internal RC Oscil-lator. This byte resides in the high byte of address 0x000. During reset, this byte isautomatically written into the OSCCAL Register to ensure correct frequency of the cali-brated RC Oscillator. Page Size Table 46. No. of Words in a Page and No. of Pages in the Flash Flash Size512 words (1K byte) Page Size16 words PCWORDPC[3:0] No. of Pages 32 PCPAGEPC[8:4] PCMSB 8 Table 47. No. of Words in a Page and No. of Pages in the EEPROM EEPROM Size bytes Page Size4 bytes PCWORDEEA[1:0] No. of Pages 16 PCPAGEEEA[5:2] EEAMSB 5 106 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 Serial Downloading Both the Flash and EEPROM memory arrays can be programmed using the serial SPIbus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI(input) and MISO (output). After RESET is set low, the Programming Enable instructionneeds to be executed first before program/erase operations can be executed. NOTE, inTable 48 on page 107, the pin mapping for SPI programming is listed. Not all parts usethe SPI pins dedicated for the internal SPI interface.Figure . Serial Programming and Verify(1) +1.8 - 5.5VRESETPB5VCCPB2SCKPB1MISOGNDPB0MOSINotes: 1.If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the CLKI pin. Table 48. Pin Mapping Serial Programming SymbolMOSIMISOSCK PinsPB0PB1PB2 I/OIOI DescriptionSerial Data inSerial Data outSerial Clock When programming the EEPROM, an auto-erase cycle is built into the self-timed pro-gramming operation (in the Serial mode ONLY) and there is no need to first execute theChip Erase instruction. The Chip Erase operation turns the content of every memorylocation in both the Program and EEPROM arrays into 0xFF. Depending on CKSEL Fuses, a valid clock must be present. The minimum low and highperiods for the serial clock (SCK) input are defined as follows: Low:> 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHzHigh:> 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz 107 2535G–AVR–01/07 元器件交易网www.cecb2b.com Serial Programming Algorithm When writing serial data to the ATtiny13, data is clocked on the rising edge of SCK.When reading data from the ATtiny13, data is clocked on the falling edge of SCK. SeeFigure 55 and Figure 56 for timing details. To program and verify the ATtiny13 in the Serial Programming mode, the followingsequence is recommended (see four byte instruction formats in Table 50): 1.Power-up sequence: Apply power between VCC and GND while RESET and SCK are set to “0”. Insome systems, the programmer can not guarantee that SCK is held low duringpower-up. In this case, RESET must be given a positive pulse of at least twoCPU clock cycles duration after SCK has been set to “0”.2.Wait for at least 20 ms and enable serial programming by sending the Program-ming Enable serial instruction to pin MOSI.3.The serial programming instructions will not work if the communication is out of synchronization. When in sync. the second byte (0x53), will echo back whenissuing the third byte of the Programming Enable instruction. Whether the echois correct or not, all four bytes of the instruction must be transmitted. If the 0x53did not echo back, give RESET a positive pulse and issue a new ProgrammingEnable command. 4.The Flash is programmed one page at a time. The memory page is loaded one byte at a time by supplying the 4 LSB of the address and data together with theLoad Program memory Page instruction. To ensure correct loading of the page,the data low byte must be loaded before data high byte is applied for a givenaddress. The Program memory Page is stored by loading the Write Programmemory Page instruction with the 5 MSB of the address. If polling (RDY/BSY) isnot used, the user must wait at least tWD_FLASH before issuing the next page. (SeeTable 49.) Accessing the serial programming interface before the Flash writeoperation completes can result in incorrect programming.5.A: The EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction. An EEPROMmemory location is first automatically erased before new data is written. If polling(RDY/BSY) is not used, the user must wait at least tWD_EEPROM before issuing thenext byte. (See Table 49.) In a chip erased device, no 0xFFs in the data file(s)need to be programmed. B: The EEPROM array is programmed one page at a time. The Memory page isloaded one byte at a time by supplying the 2 LSB of the address and datatogether with the Load EEPROM Memory Page instruction. The EEPROM Mem-ory Page is stored by loading the Write EEPROM Memory Page Instruction withthe 4 MSB of the address. When using EEPROM page access only byte loca-tions loaded with the Load EEPROM Memory Page instruction is altered. Theremaining locations remain unchanged. If polling (RDY/BSY) is not used, the usedmust wait at least tWD_EEPROM before issuing the next page (See Table 47). In achip erased device, no 0xFF in the data file(s) need to be programmed.6.Any memory location can be verified by using the Read instruction which returns the content at the selected address at serial output MISO.7.At the end of the programming session, RESET can be set high to commencenormal operation.8.Power-off sequence (if needed): Set RESET to “1”.Turn VCC power off. 108 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 Table 49. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location SymboltWD_FLASHtWD_EEPROMtWD_ERASEtWD_FUSE Minimum Wait Delay 4.5 ms4.0 ms4.0 ms4.5 ms Figure 55. Serial Programming Waveforms SERIAL DATA INPUT (MOSI)SERIAL DATA OUTPUT(MISO)SERIAL CLOCK INPUT(SCK)SAMPLEMSBLSBMSBLSB109 2535G–AVR–01/07 元器件交易网www.cecb2b.com Table 50. Serial Programming Instruction Set Instruction Format Instruction Programming EnableChip Erase Read Program MemoryLoad Program Memory Page Byte 11010 11001010 11000010 H0000100 H000 Byte 20101 0011100x xxxx0000 000a000x xxxx Byte 3xxxx xxxxxxxx xxxxbbbb bbbbxxxx bbbb Byte4xxxx xxxxxxxx xxxxoooo ooooiiii iiii Operation Enable Serial Programming after RESET goes low.Chip Erase EEPROM and Flash.Read H (high or low) data o from Program memory at word address a:b.Write H (high or low) data i to Program memory page at word address b. Data low byte must be loaded before Data high byte is applied within the same address. Write Program memory Page at address a:b. Read data o from EEPROM memory at address b. Write data i to EEPROM memory at address b. Load data i to EEPROM memory page buffer. After data is loaded, program EEPROM page. Write EEPROM page at address b. 0101 1000 0000 0000 xxxx xxxx xxoo oooo Read Lock bits. “0” = programmed, “1” = unprogrammed. See Table 42 on page 103 for details. Write Lock bits. Set bits = “0” to program Lock bits. See Table 42 on page 103 for details. Read Signature Byte o at address b.Set bits = “0” to program, “1” to unprogram. Set bits = “0” to program, “1” to unprogram. See Table 36 on page 85 for details. Read Fuse bits. “0” = programmed, “1” = unprogrammed. Read Fuse High bits. “0” = pro-grammed, “1” = unprogrammed. See Table 36 on page 85 for details.Read Calibration Byte If o = “1”, a programming operation is still busy. Wait until this bit returns to “0” before applying another command. Write Program Memory PageRead EEPROM MemoryWrite EEPROM MemoryLoad EEPROM Memory Page (page access)Write EEPROM Memory Page (page access)Read Lock bits 0100 11001010 00001100 00001100 0001 0000 000a000x xxxx000x xxxx0000 0000 bbbb xxxxxxbb bbbbxxbb bbbb0000 00bb xxxx xxxxoooo ooooiiii iiiiiiii iiii 1100 001000xx xxxxxxbb bb00xxxx xxxx Write Lock bits1010 1100111x xxxxxxxx xxxx11ii iiii Read Signature ByteWrite Fuse bitsWrite Fuse High bits 0011 00001010 11001010 1100 000x xxxx1010 00001010 1000 xxxx xxbbxxxx xxxxxxxx xxxx oooo ooooiiii iiiiiiii iiii Read Fuse bitsRead Fuse High bits 0101 00000101 1000 0000 00000000 1000 xxxx xxxxxxxx xxxx oooo oooooooo oooo Read Calibration BytePoll RDY/BSY0011 10001111 0000 000x xxxx0000 0000 0000 0000xxxx xxxx oooo ooooxxxx xxxo Note:a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care 110 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 Serial Programming Characteristics Figure 56. Serial Programming Timing MOSItOVSHSCKMISOtSHSLtSHOXtSLSHTable 51. Serial Programming Characteristics, TA = -40°C to 85°C, VCC = 1.8 - 5.5V(Unless Otherwise Noted) Symbo l1/tCLCLtCLCL1/tCLCLtCLCL1/tCLCLtCLCLtSHSLtSLSHtOVSHtSHOXNote: Parameter Oscillator Frequency (ATtiny13V, VCC = 1.8 - 5.5V) Oscillator Period (ATtiny13V, VCC = 1.8 - 5.5V)Oscillator Frequency (ATtiny13, VCC = 2.7 - 5.5V) Oscillator Period (ATtiny13, VCC = 2.7 - 5.5V)Oscillator Frequency (ATtiny13, VCC = 4.5V - 5.5V) Oscillator Period (ATtiny13, VCC = 4.5V - 5.5V)SCK Pulse Width HighSCK Pulse Width LowMOSI Setup to SCK HighMOSI Hold after SCK High 1.2 tCLCL for fck < 12 MHz, 3 tCLCL for fck >= 12 MHz Min0100001040672 tCLCL(1)2 tCLCL(1)tCLCL2 tCLCL 169.6 Typ Max1 UnitsMHznsMHznsMHznsnsnsnsns 111 2535G–AVR–01/07 元器件交易网www.cecb2b.com High-voltage Serial Programming This section describes how to program and verify Flash Program memory, EEPROMData memory, Lock bits and Fuse bits in the ATtiny13.Figure 57. High-voltage Serial Programming +11.5 - 12.5VPB5(RESET)SCI+1.8 - 5.5VVCCPB2SDOPB3PB1SIIGNDPB0SDITable 52. Pin Name Mapping Signal Name in High-voltage Serial Programming ModeSDISIISDOSCI Pin NamePB0PB1PB2PB3 I/OIIOI FunctionSerial Data InputSerial Instruction InputSerial Data Output Serial Clock Input (min. 220ns period) The minimum period for the Serial Clock Input (SCI) during High-voltage Serial Pro-gramming is 220 ns. Table 53. Pin Values Used to Enter Programming Mode PinSDISIISDO SymbolProg_enable[0]Prog_enable[1]Prog_enable[2] Value000 112 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 High-voltage Serial Programming Algorithm Enter High-voltage Serial Programming Mode To program and verify the ATtiny13 in the High-voltage Serial Programming mode, thefollowing sequence is recommended (See instruction formats in Table 55):The following algorithm puts the device in High-voltage Serial Programming mode:1.Apply 4.5 - 5.5V between VCC and GND. 2.Set RESET pin to “0” and toggle SCI at least six times.3.Set the Prog_enable pins listed in Table 53 to “000” and wait at least 100 ns. 4.Apply VHVRST - 12.5V to RESET. Keep the Prog_enable pins unchanged for at least tHVRST after the High-voltage has been applied to ensure the Prog_enablesignature has been latched.5.Shortly after latching the Prog_enable signature, the device will actively output data on the Prog_enable[2]/SDO pin, and the resulting drive contention mayincrease the power consumption. To minimize this drive contention, release theProg_enable[2] pin after tHVRST has elapsed.6.Wait at least 50 µs before giving any serial instructions on SDI/SII. Note: If the RESET pin is disabled by programming the RSTDISBL Fuse, it may not be possibleto follow the proposed algorithm above.The same may apply when External Crystal orExternal RC configuration is selected because it is not possible to apply qualified CLKIpulses. In such cases, the following algorithm should be followed: 1.Set Prog_enable pins listed in Table 53 to “000”. 2.Apply 4.5 - 5.5V between VCC and GND simultanously as 11.5 - 12.5V is applied to RESET.3.Wait 100 ns. 4.Re-program the fuses to ensure that External Clock is selected as clock source (CKSEL1:0 = 0b00) and RESET pin is activated (RSTDISBL unprogrammed). If Lock bits are programmed, a Chip Erase command must be executed before changing the fuses.5.Exit Programming mode by power the device down or by bringing RESET pin to 0b0.6.Enter Programming mode with the original algorithm, as described above.Table . High-voltage Reset Characteristics Supply VoltageVCC4.5V5.5V RESET Pin High-voltage Threshold VHVRST12V12 Minimum High-voltage Period for Latching Prog_enable tHVRST100 ns100 ns Considerations for Efficient ProgrammingThe loaded command and address are retained in the device during programming. Forefficient programming, the following should be considered.••• The command needs only be loaded once when writing or reading multiple memory locations. Skip writing the data value 0xFF that is the contents of the entire EEPROM (unless the EESAVE Fuse is programmed) and Flash after a Chip Erase. Address High byte needs only be loaded before programming or reading a new 256 word window in Flash or 256 byte EEPROM. This consideration also applies to Signature bytes reading. 113 2535G–AVR–01/07 元器件交易网www.cecb2b.com Chip Erase The Chip Erase will erase the Flash and EEPROM(1) memories plus Lock bits. The Lockbits are not reset until the Program memory has been completely erased. The Fuse bitsare not changed. A Chip Erase must be performed before the Flash and/or EEPROMare re-programmed. Note: 1.The EEPROM memory is preserved during Chip Erase if the EESAVE Fuse is programmed. 1.Load command “Chip Erase” (see Table 55). 2.Wait after Instr. 3 until SDO goes high for the “Chip Erase” cycle to finish.3.Load Command “No Operation”. 114 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 Programming the Flash The Flash is organized in pages, see Table 50 on page 110. When programming theFlash, the program data is latched into a page buffer. This allows one page of programdata to be programmed simultaneously. The following procedure describes how to pro-gram the entire Flash memory: 1.Load Command “Write Flash” (see Table 55).2.Load Flash Page Buffer. 3.Load Flash High Address and Program Page. Wait after Instr. 3 until SDO goes high for the “Page Programming” cycle to finish.4.Repeat 2 through 3 until the entire Flash is programmed or until all data has been programmed.5.End Page Programming by Loading Command “No Operation”. When writing or reading serial data to the ATtiny13, data is clocked on the rising edge ofthe serial clock, see Figure 59, Figure 60 and Table 56 for details.Figure 58. Addressing the Flash which is Organized in Pages PROGRAMCOUNTERPCMSBPCPAGEPAGEMSBPCWORDPAGE ADDRESSWITHIN THE FLASHPROGRAM MEMORYPAGEWORD ADDRESSWITHIN A PAGEPAGEINSTRUCTION WORDPCWORD[PAGEMSB:0]:000102PAGEENDFigure 59. High-voltage Serial Programming Waveforms SDIPB0SIIPB1MSBLSBMSBLSBSDOPB2MSBLSBSCIPB30123456710115 2535G–AVR–01/07 元器件交易网www.cecb2b.com Programming the EEPROM The EEPROM is organized in pages, see Table 51 on page 111. When programmingthe EEPROM, the data is latched into a page buffer. This allows one page of data to beprogrammed simultaneously. The programming algorithm for the EEPROM Data mem-ory is as follows (refer to Table 55):1.Load Command “Write EEPROM”.2.Load EEPROM Page Buffer. 3.Program EEPROM Page. Wait after Instr. 2 until SDO goes high for the “Page Programming” cycle to finish.4.Repeat 2 through 3 until the entire EEPROM is programmed or until all data has been programmed.5.End Page Programming by Loading Command “No Operation”. Reading the FlashThe algorithm for reading the Flash memory is as follows (refer to Table 55):1.Load Command \"Read Flash\". 2.Read Flash Low and High Bytes. The contents at the selected address are avail-able at serial output SDO. Reading the EEPROMThe algorithm for reading the EEPROM memory is as follows (refer to Table 55):1.Load Command “Read EEPROM”. 2.Read EEPROM Byte. The contents at the selected address are available at serial output SDO. Programming and Reading the Fuse and Lock BitsReading the Signature Bytes and Calibration BytePower-off sequence The algorithms for programming and reading the Fuse Low/High bits and Lock bits areshown in Table 55. The algorithms for reading the Signature bytes and Calibration byte are shown in Table55. Set SCI to “0”. Set RESET to “1”. Turn VCC power off. 116 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 Table 55. High-voltage Serial Programming Instruction Set for ATtiny13 Instruction Format Instruction SDI Chip Erase SIISDO Load “Write Flash” Command SDISIISDOSDISII Load Flash Page Buffer SDOSDISIISDO Instr.1/5 0_1000_0000_000_0100_1100_00x_xxxx_xxxx_xx0_0001_0000_000_0100_1100_00x_xxxx_xxxx_xx0_ bbbb_bbbb _000_0000_1100_00x_xxxx_xxxx_xx0_0000_0000_000_0111_1100_00x_xxxx_xxxx_xx Instr.2/6 0_0000_0000_000_0110_0100_00x_xxxx_xxxx_xx Instr.3 0_0000_0000_000_0110_1100_00x_xxxx_xxxx_xx Instr.4Operation Remarks Wait after Instr.3 until SDO goes high for the Chip Erase cycle to finish. Enter Flash Programming code.Repeat after Instr. 1 - 5 until the entire page buffer is filled or until all data within the page is filled. See Note 1. Instr 5. Wait after Instr 3 until SDO goes high. Repeat Instr. 2 - 3 for each loaded Flash Page until the entire Flash or all data is programmed. Repeat Instr. 1 for a new 256 byte page. See Note 1.Enter Flash Read mode. 0_0000_000a_000_0001_1100_00x_xxxx_xxxx_xx0_0000_0000_000_0111_1100_00p_pppp_pppx_xx Enter EEPROM Programming mode. 0_eeee_eeee_000_0010_1100_00x_xxxx_xxxx_xx0_0000_0000_000_0110_1100_00x_xxxx_xxxx_xx0_eeee_eeee_000_0010_1100_00x_xxxx_xxxx_xx 0_0000_0000_000_0110_1101_00x_xxxx_xxxx_xx 0_0000_0000_000_0110_0100_00x_xxxx_xxxx_xx 0_0000_0000_000_0110_1101_00x_xxxx_xxxx_xx 0_0000_0000_000_0110_1100_00x_xxxx_xxxx_xx Repeat Instr. 1 - 4 until the entire page buffer is filled or until all data within the page is filled. See Note 2. Wait after Instr. 2 until SDO goes high. Repeat Instr. 1 - 2 for each loaded EEPROM page until the entire EEPROM or all data is programmed. Repeat Instr. 1 - 5 for each new address. Wait after Instr. 5 until SDO goes high. See Note 3.Instr 5 - 6. 0_0000_0000_000_0110_1000_00x_xxxx_xxxx_xx 0_0000_0000_000_0110_1100_00q_qqqq_qqqx_xx 0_eeee_eeee_000_0010_1100_00x_xxxx_xxxx_xx 0_dddd_dddd_000_0011_1100_00x_xxxx_xxxx_xx 0_0000_0000_000_0111_1101_00x_xxxx_xxxx_xx Load Flash High SDIAddress and SIIProgram PageSDO 0_0000_000a_000_0001_1100_00x_xxxx_xxxx_xx 0_0000_0000_000_0110_0100_00x_xxxx_xxxx_xx 0_0000_0000_000_0110_1100_00x_xxxx_xxxx_xx Load “Read Flash” Command SDISIISDOSDISII 0_0000_0010_000_0100_1100_00x_xxxx_xxxx_xx0_bbbb_bbbb_000_0000_1100_00x_xxxx_xxxx_xx0_0000_0000_000_0111_1000_00x_xxxx_xxxx_xx0_0001_0001_000_0100_1100_00x_xxxx_xxxx_xx0_00bb_bbbb_000_0000_1100_00x_xxxx_xxxx_xx0_0000_0000_000_0110_0100_00x_xxxx_xxxx_xx0_00bb_bbbb_000_0000_1100_00x_xxxx_xxxx_xx0_0000_0000_000_0110_1100_00x_xxxx_xxxx_xx Instr. 5 Repeat Instr. 1, 3 - 6 for each new address. Repeat Instr. 2 for a new 256 byte page. Read Flash Low SDOand High BytesSDI SIISDO Load “Write EEPROM” Command SDISIISDOSDI Load EEPROM SII Page Buffer SDO SDISIISDOSDISII Write EEPROM SDOByteSDI SIISDO Program EEPROM Page 117 2535G–AVR–01/07 元器件交易网www.cecb2b.com Table 55. High-voltage Serial Programming Instruction Set for ATtiny13 (Continued) Instruction Format Instruction Load “Read EEPROM” Command SDISIISDO Instr.1/5 0_0000_0011_000_0100_1100_00x_xxxx_xxxx_xx0_bbbb_bbbb_000_0000_1100_00x_xxxx_xxxx_xx0_0100_0000_000_0100_1100_00x_xxxx_xxxx_xx0_0100_0000_000_0100_1100_00x_xxxx_xxxx_xx0_0010_0000_000_0100_1100_00x_xxxx_xxxx_xx0_0000_0100_000_0100_1100_00x_xxxx_xxxx_xx0_0000_0100_000_0100_1100_00x_xxxx_xxxx_xx0_0000_0100_000_0100_1100_00x_xxxx_xxxx_xx0_0000_1000_000_0100_1100_00x_xxxx_xxxx_xx0_0000_1000_000_0100_1100_00x_xxxx_xxxx_xx0_0000_0000_000_0100_1100_00x_xxxx_xxxx_xx Instr.2/6Instr.3Instr.4Operation Remarks Enter EEPROM Read mode. SDI Read EEPROM SII Byte SDOSDI Write Fuse Low SII Bits SDOSDI Write Fuse High SII Bits SDO SDI Write Lock Bits SIISDO SDI Read Fuse Low SII Bits SDOSDI Read Fuse High SII Bits SDO SDI Read Lock Bits SIISDO SDI Read Signature SII Bytes SDOSDI Read SII Calibration Byte SDOLoad “No Operation” Command SDISIISDO 0_aaaa_aaaa_000_0001_1100_00x_xxxx_xxxx_xx0_A987_63_000_0010_1100_00x_xxxx_xxxx_xx0_000F_EDCB_000_0010_1100_00x_xxxx_xxxx_xx0_0000_0021_000_0010_1100_00x_xxxx_xxxx_xx0_0000_0000_000_0110_1000_00x_xxxx_xxxx_xx0_0000_0000_000_0111_1010_00x_xxxx_xxxx_xx0_0000_0000_000_0111_1000_00x_xxxx_xxxx_xx0_0000_00bb_000_0000_1100_00x_xxxx_xxxx_xx0_0000_0000_000_0000_1100_00x_xxxx_xxxx_xx 0_0000_0000_000_0110_1000_00x_xxxx_xxxx_xx0_0000_0000_000_0110_0100_00x_xxxx_xxxx_xx0_0000_0000_000_0111_0100_00x_xxxx_xxxx_xx0_0000_0000_000_0110_0100_00x_xxxx_xxxx_xx0_0000_0000_000_0110_1100_00A_9876_3x_xx0_0000_0000_000_0111_1110_00x_xxFE_DCBx_xx0_0000_0000_000_0111_1100_00x_xxxx_x21x_xx0_0000_0000_000_0110_1000_00x_xxxx_xxxx_xx0_0000_0000_000_0111_1000_00x_xxxx_xxxx_xx 0_0000_0000_000_0110_1100_00q_qqqq_qqq0_000_0000_0000_000_0110_1100_00x_xxxx_xxxx_xx0_0000_0000_000_0111_1100_00x_xxxx_xxxx_xx0_0000_0000_000_0110_1100_00x_xxxx_xxxx_xx Repeat Instr. 1, 3 - 4 for each new address. Repeat Instr. 2 for a new 256 byte page. Wait after Instr. 4 until SDO goes high. Write A - 3 = “0” to program the Fuse bit. Wait after Instr. 4 until SDO goes high. Write F - B = “0” to program the Fuse bit. Wait after Instr. 4 until SDO goes high. Write 2 - 1 = “0” to program the Lock Bit. Reading A - 3 = “0” means the Fuse bit is programmed. Reading F - B = “0” means the Fuse bit is programmed. Reading 2, 1 = “0” means the Lock bit is programmed. 0_0000_0000_000_0110_1100_00q_qqqq_qqqx_xx0_0000_0000_000_0111_1100_00p_pppp_pppx_xx Repeats Instr 2 4 for each signature byte address. Note:a = address high bits, b = address low bits, d = data in high bits, e = data in low bits, p = data out high bits, q = data out low bits,x = don’t care, 1 = Lock Bit1, 2 = Lock Bit2, 3 = CKSEL0 Fuse, 4 = CKSEL1 Fuse, 5 = SUT0 Fuse, 6 = SUT1 Fuse, 7 = CKDIV8,Fuse, 8 = WDTON Fuse, 9 = EESAVE Fuse, A = SPIEN Fuse, B = RSTDISBL Fuse, C = BODLEVEL0 Fuse, D= BODLEVEL1Fuse, E = MONEN Fuse, F = SELFPRGEN Fuse 1.For page sizes less than 256 words, parts of the address (bbbb_bbbb) will be parts of the page address.2.For page sizes less than 256 bytes, parts of the address (bbbb_bbbb) will be parts of the page address. 3.The EEPROM is written page-wise. But only the bytes that are loaded into the page are actually written to the EEPROM. Page-wise EEPROM access is more efficient when multiple bytes are to be written to the same page. Note that auto-eraseof EEPROM is not available in High-voltage Serial Programming, only in SPI Programming. Notes: 118 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 High-voltage Serial Programming Characteristics Figure 60. High-voltage Serial Programming Timing CCCKTable 56. High-voltage Serial Programming Characteristics VCC = 5.0V ± 10% (Unlessotherwise noted) SymboltSHSLtSLSHtIVSHtSHIXtSHOVtWLWH_PFB Parameter SCI (PB3) Pulse Width HighSCI (PB3) Pulse Width Low SDI (PB0), SII (PB1) Valid to SCI (PB3) HighSDI (PB0), SII (PB1) Hold after SCI (PB3) HighSCI (PB3) High to SDO (PB2) ValidWait after Instr. 3 for Write Fuse Bits Min1101105050 162.5Typ Max Unitsnsnsnsnsnsms 119 2535G–AVR–01/07 元器件交易网www.cecb2b.com Electrical Characteristics Absolute Maximum Ratings* Operating Temperature..................................-55°C to +125°CStorage Temperature.....................................-65°C to +150°CVoltage on any Pin except RESETwith respect to Ground................................-0.5V to VCC+0.5VVoltage on RESET with respect to Ground......-0.5V to +13.0VMaximum Operating Voltage............................................6.0VDC Current per I/O Pin...............................................40.0 mADC Current VCC and GND Pins................................200.0 mA *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam-age to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics TA = -40°C to 85°C, VCC = 1.8V to 5.5V (unless otherwise noted)(1) SymbolVILVIHVIL1VIH1VIL2VIH2VIL3VIH3VOLVOL1 Parameter Input Low Voltage except RESET pinInput High-voltage except RESET pinInput Low-voltageCLKI pin Input High-voltageCLKI pin Input Low-voltageRESET pinInput High-voltageRESET pinInput Low-voltageRESET pinInput High-voltageRESET pinOutput Low Voltage(4)(PB1 and PB0) Output Low Voltage(4) (PB5, PB4, PB3 and PB2)Output Low Voltage (PB5, Reset used as I/O)Output High-voltage(5)( PB1 and PB0) (4) ConditionVCC = 1.8V - 2.4VVCC = 2.4V - 5.5VVCC = 1.8V - 2.4VVCC = 2.4V - 5.5VVCC = 1.8V - 5.5VCC = 1.8V - 2.4VVCC = 2.4V - 5.5VVCC = 1.8V - 5.5VCC = 1.8V - 5.5VCC = 1.8V - 2.4VVCC = 2.4V - 5.5VVCC = 1.8V - 2.4VVCC = 2.4V - 5.5VIOL = 20 mA, VCC = 5VIOL = 10 mA, VCC = 3VIOL = 10 mA, VCC = 5VIOL = 5 mA, VCC = 3VIOL =TBD mA, VCC = TBDV IOL =TBD mA, VCC = TBDV IOH = -20 mA, VCC = 5VIOH = -10 mA, VCC = 3V Min.-0.50.7VCC(3)0.6VCC(3) -0.50.8VCC(3)0.7VCC(3) -0.50.9VCC(3) -0.50.7VCC(3)0.6VCC(3) Typ.Max.0.2VCC0.3VCCVCC +0.50.1VCCVCC +0.50.2VCCVCC +0.50.2VCCVCC +0.50.70.50.70.5 UnitsVVVVVVVVVVVVVV VOL2 VOH 4.22.5VV 120 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 TA = -40°C to 85°C, VCC = 1.8V to 5.5V (unless otherwise noted)(1) (Continued) SymbolVOH1 Parameter Output High-voltage(5)(PB4, PB3 and PB2)Output High-voltage (PB5, Reset used as I/O)Input LeakageCurrent I/O PinInput LeakageCurrent I/O PinReset Pull-up ResistorI/O Pin Pull-up Resistor Active 1MHz, VCC = 2VActive 4MHz, VCC = 3V Power Supply Current ICC Active 8MHz, VCC = 5VIdle 1MHz, VCC = 2VIdle 4MHz, VCC = 3VIdle 8MHz, VCC = 5V Power-down mode VACIOIACLKtACPDNotes: Analog Comparator Input Offset Voltage Analog Comparator Input Leakage CurrentAnalog Comparator Propagation Delay WDT enabled, VCC = 3VWDT disabled, VCC = 3VVCC = 5VVin = VCC/2VCC = 5VVin = VCC/2VCC = 2.7VVCC = 4.0V -50 7505000.080.411.6< 5< 0.5< 10 (5) Condition IOH = -10 mA, VCC = 5VIOH = -5 mA, VCC = 3VIOH = - TBD mA, VCC = TBDV IOH = - TBD mA, VCC = TBDV Vcc = 5.5V, pin low(absolute value)Vcc = 5.5V, pin high(absolute value) Min.4.22.5 Typ.Max.UnitsVVVV VOH2 IILIIHRRSTRpu 11 3020 80500.351.860.2131024050 µAµAkΩkΩmAmAmAmAmAmAµAµAmVnAns 1.All DC Characteristics contained in this data sheet are based on simulation and characterization of other AVR microcontrol-lers manufactured in the same process technology. These values are representing design targets, and will be updated aftercharacterization of actual silicon. 2.“Max” means the highest value where the pin is guaranteed to be read as low.3.“Min” means the lowest value where the pin is guaranteed to be read as high. 4.Although each I/O port can sink more than the test conditions (20 mA at VCC = 5V, 10 mA at VCC = 3V for PB5, PB1:0, 10 mA at VCC = 5V, 5 mA at VCC = 3V for PB4:2) under steady state conditions (non-transient), the following must be observed:1] The sum of all IOL, for all ports, should not exceed 60 mA. If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greaterthan the listed test condition. 5.Although each I/O port can source more than the test conditions (20 mA at VCC = 5V, 10 mA at VCC = 3V for PB5, PB1:0, 10 mA at VCC = 5V, 5 mA at VCC = 3V for PB4:2) under steady state conditions (non-transient), the following must be observed:1] The sum of all IOH, for all ports, should not exceed 60 mA. If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source currentgreater than the listed test condition. 121 2535G–AVR–01/07 元器件交易网www.cecb2b.com External Clock Drive Waveforms Figure 61. External Clock Drive Waveforms VIH1VIL1External Clock Drive Table 57. External Clock Drive VCC = 1.8 - 5.5V Symbol1/tCLCLtCLCLtCHCXtCLCXtCLCHtCHCL ParameterClock FrequencyClock PeriodHigh TimeLow TimeRise TimeFall Time Change in period from one clock cycle to the next Min.01000400400 2.02.02Max.4 VCC = 2.7 - 5.5VMin.01045050 1.61.62Max.10 VCC = 4.5 - 5.5VMin.062.52525 0.50.52Max.20 UnitsMHznsnsnsµsµs% ΔtCLCL 122 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 Maximum Speed vs. VCC Maximum frequency is dependent on VCC. As shown in Figure 62 and Figure 63, theMaximum Frequency vs. VCC curve is linear between 1.8V < VCC < 2.7V and between2.7V < VCC < 4.5V. Figure 62. Maximum Frequency vs. VCC, ATtiny13V 10 MHzSafe Operating Area4 MHz1.8V2.7V5.5VFigure 63. Maximum Frequency vs. VCC, ATtiny13 20 MHz10 MHzSafe Operating Area2.7V4.5V5.5V2535G–AVR–01/07 123 元器件交易网www.cecb2b.com ADC Characteristics Table 58. ADC Characteristics, Single Ended Channels. -40°C - 85°C Symbol ParameterResolution Condition Single Ended ConversionSingle Ended ConversionVREF = 4V, VCC = 4V,ADC clock = 200 kHzSingle Ended ConversionVREF = 4V, VCC = 4V,ADC clock = 1 MHzSingle Ended ConversionVREF = 4V, VCC = 4V,ADC clock = 200 kHzNoise Reduction ModeSingle Ended ConversionVREF = 4V, VCC = 4V,ADC clock = 1 MHzNoise Reduction Mode Integral Non-linearity (INL) Single Ended ConversionVREF = 4V, VCC = 4V,ADC clock = 200 kHzSingle Ended ConversionVREF = 4V, VCC = 4V,ADC clock = 200 kHzSingle Ended ConversionVREF = 4V, VCC = 4V,ADC clock = 200 kHzSingle Ended ConversionVREF = 4V, VCC = 4V,ADC clock = 200 kHzFree Running Conversion 1350GND 38.5 1.0 1.1100 1.2 2 Min Typ Max10 UnitsBitsLSB 3LSB Absolute accuracy (Including INL, DNL, quantization error, gain and offset error) 1.5LSB 2.5LSB 1LSB Differential Non-linearity (DNL)0.5LSB Gain Error2.5LSB Offset ErrorConversion TimeClock Frequency VIN Input VoltageInput Bandwidth VINTRAIN Internal Voltage ReferenceAnalog Input Resistance 1.5 2601000VREF LSBµskHzVkHzVMΩ 124 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 Typical Characteristics The following charts show typical behavior. These figures are not tested during manu-facturing. All current consumption measurements are performed with all I/O pinsconfigured as inputs and with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock source. The power consumption in Power-down mode is independent of clock selection.The current consumption is a function of several factors such as: operating voltage,operating frequency, loading of I/O pins, switching rate of I/O pins, code executed andambient temperature. The dominating factors are operating voltage and frequency.The current drawn from capacitive loaded pins may be estimated (for one pin) asCL*VCC*f where CL = load capacitance, VCC = operating voltage and f = average switch-ing frequency of I/O pin. The parts are characterized at frequencies higher than test limits. Parts are not guaran-teed to function properly at frequencies higher than the ordering code indicates.The difference between current consumption in Power-down mode with WatchdogTimer enabled and Power-down mode with Watchdog Timer disabled represents the dif-ferential current drawn by the Watchdog Timer. Active Supply Current Figure . Active Supply Current vs. Frequency (0.1 - 1.0 MHz) ACTIVE SUPPLY CURRENT vs. LOW FREQUENCY0.1 - 1.0 MHz1.215.5 V5.0 V0.8ICC (mA)4.5 V4.0 V3.3 V0.60.42.7 V1.8 V0.2000.10.20.30.40.50.60.70.80.91Frequency (MHz)125 2535G–AVR–01/07 元器件交易网www.cecb2b.com Figure 65. Active Supply Current vs. Frequency (1 - 20 MHz) ACTIVE SUPPLY CURRENT vs. FREQUENCY1 - 20MHz145.5 V125.0 V10ICC (mA)4.5 V824.0 V3.3 V2.7 V1.8 V00246810Frequency (MHz)1214161820Figure 66. Active Supply Current vs. VCC (Internal RC Oscillator, 9.6 MHz) ACTIVE SUPPLY CURRENT vs. VCCINTERNAL RC OSCILLATOR, 9.6 MHz8765ICC (mA)85 °C-40 °C25 °C432101.522.533.4.555.5VCC (V)126 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 Figure 67. Active Supply Current vs. VCC (Internal RC Oscillator, 4.8 MHz) ACTIVE SUPPLY CURRENT vs. VCCINTERNAL RC OSCILLATOR, 4.8 MHz4.3.53ICC (mA)25 °C-40 °C85 °C2.521.510.501.522.533.4.555.5VCC (V)Figure 68. Active Supply Current vs. VCC (Internal WDT Oscillator, 128 kHz) ACTIVE SUPPLY CURRENT vs. VCCINTERNAL WD OSCILLATOR, 128 KHz0.140.120.10.080.060.040.0201.522.533.4.555.5-40 °C25 °C85 °CICC (mA)VCC (V)127 2535G–AVR–01/07 元器件交易网www.cecb2b.com Figure 69. Active Supply Current vs. VCC (32 kHz External Clock) ACTIVE SUPPLY CURRENT vs. VCC32 kHz EXTERNAL CLOCK0.040.0350.030.025ICC (mA)25 °C85 °C0.020.0150.010.00501.522.533.4.555.5VCC (V)Idle Supply Current Figure 70. Idle Supply Current vs. Frequency (0.1 - 1.0 MHz) IDLE SUPPLY CURRENT vs. LOW FREQUENCY(0.1 - 1.0 MHz)0.90.80.70.65.5 V5.0 V4.5 V4.0 V3.3 V2.7 V1.8 VICC (mA)0.50.40.30.20.1000.10.20.30.40.50.60.70.80.91Frequency (MHz)128 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 Figure 71. Idle Supply Current vs. Frequency (1 - 20 MHz) IDLE SUPPLY CURRENT vs. FREQUENCY1 - 20MHz.3.53ICC (mA)5.5 V5.0 V4.5 V2.521.510.50024.0 V3.3 V2.7 V1.8 V468101214161820Frequency (MHz)Figure 72. Idle Supply Current vs. VCC (Internal RC Oscillator, 9.6 MHz) IDLE SUPPLY CURRENT vs. VCCINTERNAL RC OSCILLATOR, 9.6 MHz2.5285 °C25 °C-40 °CICC (mA)1.510.501.522.533.4.555.5VCC (V)129 2535G–AVR–01/07 元器件交易网www.cecb2b.com Figure 73. Idle Supply Current vs. VCC (Internal RC Oscillator, 4.8 MHz) IDLE SUPPLY CURRENT vs. VCCINTERNAL RC OSCILLATOR, 4.8 MHz1.2185 °C25 °C-40 °C0.8ICC (mA)0.60.40.201.522.533.4.555.5VCC (V)Figure 74. Idle Supply Current vs. VCC (Internal RC Oscillator, 128 kHz) IDLE SUPPLY CURRENT vs. VCCINTERNAL WD OSCILLATOR, 128 KHz0.0350.030.0250.020.0150.010.00501.522.533.4.555.5-40 °C25 °C85 °CICC (mA)VCC (V)130 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 Figure 75. Idle Supply Current vs. VCC (32 kHz External Clock) IDLE SUPPLY CURRENT vs. VCC32kHz EXTERNAL CLOCK 1098785 °C25 °C-40 °CICC (uA)632101.522.533.4.555.5VCC (V)Power-Down Supply Current Figure 76. Power-Down Supply Current vs. VCC (Watchdog Timer Disabled) POWER-DOWN SUPPLY CURRENT vs. VCCWATCHDOG TIMER DISABLED 1.81.61.41.285 ˚CICC (uA)10.80.60.40.201.522.533.4.555.5-40 ˚C25 ˚CVCC (V)131 2535G–AVR–01/07 元器件交易网www.cecb2b.com Figure 77. Power-Down Supply Current vs. VCC (Watchdog Timer Enabled) POWER-DOWN SUPPLY CURRENT vs. VCCWATCHDOG TIMER ENABLED 10987-40 ˚C85 ˚C25 ˚CICC (uA)632101.522.533.4.555.5VCC (V)Pin Pull-up Figure 78. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGEVCC = 5V16014085 ˚C12010025 ˚C-40 ˚CIOP (uA)8060402000123456VOP (V)132 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 Figure 79. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGEVCC = 2.78085 ºC25 ˚C7060-40 ˚C50A) (u40POI302010000.511.522.53VOP (V)Figure 80. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGEVCC = 5V120-40 ˚C25 ˚C10085 ˚C80)Au( TE60SERI40200012345VRESET (V)2535G–AVR–01/07 133 元器件交易网www.cecb2b.com Figure 81. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGEVCC = 2.7V60-40 ˚C5025 ˚C4085 ˚CIRESET (uA)302010000.511.522.53VRESET (V)Pin Driver Strength Figure 82. I/O Pin Source Current vs. Output Voltage (Low Power Ports, VCC = 5V) I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGELOW POWER PORTS, VCC = 5V706050-40 ˚C25 ˚C85 ˚CIOH (mA)4030201000123456VOH (V)134 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 Figure 83. I/O Pin Source Current vs. Output Voltage (Low Power Ports, VCC = 2.7V) I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGELOW POWER PORTS, VCC = 2.7V25-40 °C2025 °C85 °CIOH (mA)15105000.511.522.53VOH (V)Figure 84. I/O Pin Source Current vs. Output Voltage (Low Power Ports, VCC = 1.8V) I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGELOW POWER PORTS, VCC = 1.8V725 ˚C6-40 ˚C85 ˚C5IOH (mA)4321000.20.40.60.811.21.41.61.82VOH (V)135 2535G–AVR–01/07 元器件交易网www.cecb2b.com Figure 85. I/O Pin Sink Current vs. Output Voltage (Low Power Ports, VCC = 5V) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGELOW POWER PORTS, VCC = 5V504035-40 ˚C25 ˚C85 ˚CIOL (mA)30252015105000.511.522.5VOL (V)Figure 86. I/O Pin Sink Current vs. Output Voltage (Low Power Ports, VCC = 2.7V) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGELow Power Ports, VCC = 2.7V20181614-40 ˚C25 ˚C85 ˚CIOL (mA)121082000.511.522.5VOL (V)136 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 Figure 87. I/O Pin Sink Current vs. Output Voltage (Low Power Ports, VCC = 1.8V) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGELOW POWER PORTS, 1.8V76-40 ˚C525 ˚C85 ˚C)A4m( LOI321000.20.40.60.811.21.41.61.82VOL (V)Figure 88. I/O Pin Source Current vs. Output Voltage (VCC = 5V) I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGEVCC = 5V9080-40 ˚C706025 ˚C85 ˚C)Am50( HOI40302010023456VOH (V)2535G–AVR–01/07 137 元器件交易网www.cecb2b.com Figure . I/O Pin Source Current vs. Output Voltage (VCC = 2.7V) I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGEVCC = 2.7V353025-40 ˚C25 ˚C85 ˚CIOH (mA)2015105000.511.522.53VOH (V)Figure 90. I/O Pin Source Current vs. Output Voltage (VCC = 1.8V) I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGEVCC = 1.8V109-40 ˚C25 ˚C8785 ˚CIOH (mA)6321000.20.40.60.811.21.41.61.82VOH (V)138 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 Figure 91. I/O Pin Sink Current vs. Output Voltage (VCC = 5V) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGEVCC = 5V1009080-40 ˚C7025 ˚C85 ˚C)60Am( 50LOI40302010000.511.522.5VOL (V)Figure 92. I/O Pin Sink Current vs. Output Voltage (VCC = 2.7V) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGEVCC = 2.7V4035-40 ˚C3025 ˚C25)A85 ˚Cm( 20LOI15105000.511.522.5VOL (V)2535G–AVR–01/07 139 元器件交易网www.cecb2b.com Figure 93. I/O Pin Sink Current vs. Output Voltage (VCC = 1.8V) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGEVCC = 1.8V141210IOL (mA)-40 ˚C25 ˚C85 ˚C82000.20.40.60.81VOL (V)1.21.41.61.82Figure 94. Reset Pin as I/O - Source Current vs. Output Voltage (VCC = 5V) RESET PIN AS I/O - SOURCE CURRENT vs. OUTPUT VOLTAGEVCC = 5V1.61.4-40 ˚C1.2125 ˚C85 ˚CIOH (mA)0.80.60.40.202345VOH (V)140 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 Figure 95. Reset Pin as I/O - Source Current vs. Output Voltage (VCC = 2.7V) RESET PIN AS I/O - SOURCE CURRENT vs. OUTPUT VOLTAGEVCC = 2.7V2.5-40 ˚C225 ˚C)1.585 ˚CAm( HOI10.5000.511.522.53VOH (V)Figure 96. Reset Pin as I/O - Source Current vs. Output Voltage (VCC = 1.8V) RESET PIN AS I/O - SOURCE CURRENT vs. OUTPUT VOLTAGEVCC = 1.8V2.5-40 °C225 °C)1.5Am( HOI185 °C0.5000.20.40.60.811.21.41.61.82VOH (V)2535G–AVR–01/07 141 元器件交易网www.cecb2b.com Figure 97. Reset Pin as I/O - Sink Current vs. Output Voltage (VCC = 5V) RESET PIN AS I/O - SINK CURRENT vs. OUTPUT VOLTAGEVCC = 5V14-40 ˚C121082000.511.522.525 ˚C85 ˚CIOL (mA)VOL (V)Figure 98. Reset Pin as I/O - Sink Current vs. Output Voltage (VCC = 2.7V) RESET PIN AS I/O - SINK CURRENT vs. OUTPUT VOLTAGEVCC = 2.7V4.3.53-40 ˚C25 ˚C85 ˚CIOL (mA)2.521.510.5000.511.522.5VOL (V)142 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 Figure 99. Reset Pin as I/O - Sink Current vs. Output Voltage (VCC = 1.8V) RESET PIN AS I/O - SINK CURRENT vs. OUTPUT VOLTAGEVCC = 1.8V1.61.41.21-40 ˚C25 ˚C85 ˚CIOL (mA)0.80.60.40.2000.20.40.60.811.21.41.61.82VOL (V)Pin Thresholds and Hysteresis Figure 100. I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as '1') I/O PIN INPUT THRESHOLD VOLTAGE vs. VCCVIH, IO PIN READ AS '1'385 ˚C25 ˚C-40 ˚C2.52Threshold (V)1.510.501.522.533.4.555.5VCC (V)143 2535G–AVR–01/07 元器件交易网www.cecb2b.com Figure 101. I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as '0') I/O PIN INPUT THRESHOLD VOLTAGE vs. VCCVIL, IO PIN READ AS '0'32.585 ˚C25 ˚C-40 ˚C2Threshold (V)1.510.501.522.533.4.555.5VCC (V)Figure 102. I/O Pin Input Hysteresis vs. VCC I/O PIN INPUT HYSTERESIS vs. VCC0.450.40.35-40 ºCInput Hysteresis (V)0.30.250.225 ºC85 ºC0.150.10.0501.522.533.4.555.5VCC (V)144 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 Figure 103. Reset Pin as I/O - Input Threshold Voltage vs. VCC (VIH, Reset Pin Readas '1') RESET PIN AS I/O - THRESHOLD VOLTAGE vs. VCCVIH, IO PIN READ AS '1'32.52Threshold (V)-40 ˚C1.525 ˚C85 ˚C10.501.522.533.4.555.5VCC (V)Figure 104. Reset Pin as I/O - Input Threshold Voltage vs. VCC (VIL, Reset Pin Read as'0') RESET PIN AS I/O - THRESHOLD VOLTAGE vs. VCCVIL, IO PIN READ AS '0'2.52Threshold (V)1.585 ˚C125 ˚C0.5-40 ˚C01.522.533.4.555.5VCC (V)145 2535G–AVR–01/07 元器件交易网www.cecb2b.com Figure 105. Reset Pin as I/O - Pin Hysteresis vs. VCC RESET PIN AS IO - PIN HYSTERESIS vs. VCC0.70.6-40 ºC0.5Input Hysteresis (V)25 ºC85 ºC0.40.30.20.101.522.533.4.555.5VCC (V)Figure 106. Reset Input Threshold Voltage vs. VCC (VIH, Reset Pin Read as '1') RESET INPUT THRESHOLD VOLTAGE vs. VCCVIH, IO PIN READ AS '1'2.52Threshold (V)1.5-40 ˚C10.585 ˚C25 ˚C01.522.533.4.555.5VCC (V)146 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 Figure 107. Reset Input Threshold Voltage vs. VCC (VIL, Reset Pin Read as '0') RESET INPUT THRESHOLD VOLTAGE vs. VCCVIL, IO PIN READ AS '0'2.52)V(1.5 dlohserhT185 ˚C0.525 ˚C-40 ˚C01.522.533.4.555.5VCC (V)Figure 108. Reset Input Pin Hysteresis vs. VCC RESET INPUT THRESHOLD VOLTAGE vs. VCCVIL, IO PIN READ AS '0'0.5-40 ºC0.4)V(0.3 dlohse85 ºCrhT0.225 ºC0.101.522.533.4.555.5VCC (V)2535G–AVR–01/07 147 元器件交易网www.cecb2b.com BOD Thresholds and Analog Comparator Offset Figure 109. BOD Thresholds vs. Temperature (BODLEVEL is 4.3V) BOD THRESHOLDS vs. TEMPERATUREBODLEVEL IS 4.3V4.5Rising VCC4.4Threshold (V)4.3Falling VCC4.2-60-40-20020406080100Temperature (C)Figure 110. BOD Thresholds vs. Temperature (BODLEVEL is 2.7V) BOD THRESHOLDS vs. TEMPERATUREBODLEVEL IS 2.7V2.9Rising VCC2.8Threshold (V)2.7Falling VCC2.6-60-40-20020406080100Temperature (C)148 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 Figure 111. BOD Thresholds vs. Temperature (BODLEVEL is 1.8V) BOD THRESHOLDS vs. TEMPERATUREBODLEVEL IS 1.8V1.9Rising VCC1.85Threshold (V)1.8Falling VCC1.75-60-40-20020406080100Temperature (C)Figure 112. Bandgap Voltage vs. VCC BANDGAP VOLTAGE vs. VCC1.061.041.02Bandgap Voltage (V)85ºC25ºC10.980.960.940.921.52.53..55.5-40ºCVCC (V)149 2535G–AVR–01/07 元器件交易网www.cecb2b.com Figure 113. Analog Comparator Offset Voltage vs. Common Mode Voltage (VCC = 5V) ANALOG COMPARATOR OFFSET vs. COMMON MODE VOLTAGEVCC = 5V0.0080.007Comparator Offset Voltage (V)0.0060.0050.0040.0030.0020.001000.511.522.533.4.5585 °C25 °C-40 °CCommon Mode Voltage (V)Figure 114. Analog Comparator Offset Voltage vs. Common Mode Voltage (VCC= 2.7V) ANALOG COMPARATOR OFFSET vs. COMMON MODE VOLTAGEVCC = 2.7V0.0030.0025Comparator Offset Voltage (V)85 °C25 °C0.002-40 °C0.00150.0010.0005000.511.5Common Mode Voltage (V)22.53150 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 Internal Oscillator SpeedFigure 115. Calibrated 9.6 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 9.6 MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 10.310.19.99.7FRC (MHz)9.59.35.5 V4.5 V9.18.98.78.5-602.7 V1.8 V-40-20020406080100Temperature (C)Figure 116. Calibrated 9.6 MHz RC Oscillator Frequency vs. VCC CALIBRATED 9.6 MHz RC OSCILLATOR FREQUENCY vs. VCC1110.585 ˚C10FRC (MHz)9.525 ˚C-40 ˚C98.581.522.533.4.555.5VCC (V)151 2535G–AVR–01/07 元器件交易网www.cecb2b.com Figure 117. Calibrated 9.6 MHz RC Oscillator Frequency vs. Osccal Value CALIBRATED 9.6MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE1816141210820816243240485672808610411212025 ˚CFRC (MHz)OSCCAL VALUEFigure 118. Calibrated 4.8 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 4.8 MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE5.1.9FRC (MHz)4.84.71.8 V5.5 V4.0 V2.7 V4..5-60-40-20020Temperature (C)406080100152 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 Figure 119. Calibrated 4.8 MHz RC Oscillator Frequency vs. VCC CALIBRATED 4.8 MHz RC OSCILLATOR FREQUENCY vs. VCC5.285 ˚C5FRC (MHz)4.825 ˚C-40 ˚C4..41.522.533.4.555.5VCC (V)Figure 120. Calibrated 4.8 MHz RC Oscillator Frequency vs. Osccal Value CALIBRATED 4.8 MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE10987FRC (MHz)25 ˚C632108162432404856728086104112120 127OSCCAL VALUE153 2535G–AVR–01/07 元器件交易网www.cecb2b.com Figure 121. 128 kHz Watchdog Oscillator Frequency vs. VCC 128 kHz WATCHDOG OSCILLATOR FREQUENCY vs. VCC 120-40 ˚C115FRC (kHz)25 ˚C11010585 ˚C1001.522.533.4.555.5VCC (V)Figure 122. 128 kHz Watchdog Oscillator Frequency vs. Temperature 128 kHz WATCHDOG OSCILLATOR FREQUENCY vs. TEMPERATURE118116114112FRC (kHz)1101.8 V108106104102100-60-40-200204060801002.7 V4.0 V5.5 VTemperature (C)1 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 Current Consumption of Figure 123. Brownout Detector Current vs. VCCPeripheral Units 353025201510501.522.533.4.555.5BROWNOUT DETECTOR CURRENT vs. VCC-40 ˚C25 ˚C85 ˚CICC (uA)VCC (V)Figure 124. ADC Current vs. VCC ADC CURRENT vs. VCC350-40 ˚C30025 ˚C2502001501005001.522.533.4.555.585 ˚CICC (uA)VCC (V)155 2535G–AVR–01/07 元器件交易网www.cecb2b.com Figure 125. Analog Comparator Current vs. VCC ANALOG COMPARATOR CURRENT vs. VCC1401201008060402001.522.533.4.555.5-40 ˚C25 ˚C85 ˚CICC (uA)VCC (V)Figure 126. Programming Current vs. VCC PROGRAMMING CURRENT vs. Vcc43.532.5ICC (mA)21.510.501.522.533.4.555.5-40 °C25 °C85 °CVCC (V)156 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 Current Consumption in Figure 127. Reset Supply Current vs. VCC (0.1 - 1.0 MHz, Excluding Current through the Reset Pull-up)Reset and Reset Pulse width RESET SUPPLY CURRENT vs. VCC0.1 - 1.0 MHz, EXCLUDING CURRENT THROUGH THE RESET PULL-UP0.140.120.1ICC (mA)5.5 V5.0 V4.5 V4.0 V3.3 V2.7 V0.080.060.040.02000.10.20.30.40.50.60.70.80.91Frequency (MHz)1.8 VFigure 128. Reset Supply Current vs. VCC (1 - 24 MHz, Excluding Current through theReset Pull-up) RESET SUPPLY CURRENT vs. VCC1 - 24 MHz, EXCLUDING CURRENT THROUGH THE RESET PULL-UP3.532.521.55.5V5.0V4.5VICC (mA)4.0V13.3V0.50024681.8V10122.7V141618202224Frequency (MHz)157 2535G–AVR–01/07 元器件交易网www.cecb2b.com Figure 129. Reset Pulse Width vs. VCC RESET PULSE WIDTH vs. V2500CC2000Pulsewidth (ns)1500100050001.82.12.52.733.3VCC (V)85 ºC25 ºC-40 ºC3.4.555.56158 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 Register Summary Address 0x3F0x3E Name SREG Bit 7 I– Bit 6 T– Bit 5 H– Bit 4 S– SP[7:0]– Bit 3 V– Bit 2 N– Bit 1 Z– Bit 0 C– Page page 7page 9 Reserved DD0x3DSPL0x3C0x3B ReservedGIMSK ––––– INT0INTF0––– PCIEPCIF––– ––––CTPB ––OCIE0BOCF0BRFLB ––OCIE0AOCF0APGWRT ––TOIE0TOV0PGERS –––– SELFPRGEN page 56page 56page 73page 74page 100page 73page 51page 34page 69page 73page 23 0x3A GIFR0x39 TIMSK00x38 TIFR00x37 SPMCSR0x36 0x35 OCR0A Timer/Counter – Output Compare Register A MCUCR–PUDSESM1SM0–ISC01ISC00DDDDDDDDD0x34 MCUSR––––WDRFBORFEXTRFPORF0x33 TCCR0B0x32 0x31 TCNT0OSCCALTCCR0ADWDRReservedReservedReservedOCR0B TSMCLKPCE –– –– COM0A1 COM0A0 COM0B1 FOC0A FOC0B – – WGM02 CS02 CS01 CS00 Timer/Counter (8-bit)Oscillator Calibration Register – COM0B0 DWDR[7:0] –––– Timer/Counter – Output Compare Register B – – – –––– WTIF WTIE WP3 WCE –– –– –– EEPM1 EEPM0 ––– ––––– ––––– PORTB5DDB5PINB5PCINT5ADC0D PORTB4DDB4PINB4PCINT4ADC2D ––––––––––– ACD–ADEN ACBGREFS0ADSC ACOADLARADATE ACI–ADIF ACIE–ADIE ––ADPS2 ACIS1MUX1ADPS1 ACIS0MUX0ADPS0 PORTB3DDB3PINB3PCINT3ADC3D PORTB2DDB2PINB2PCINT2ADC1D PORTB1DDB1PINB1PCINT1AIN1D PORTB0DDB0PINB0PCINT0AIN0D EEPROM Address Register EEPROM Data Register EERIE EEMPE EEPE EERE WE WP2 WP1 WP0 CLKPS3 CLKPS2 CLKPS1 CLKPS0 – – – PSR10 – – WGM01 WGM00 0x30 Reserved0x2F0x2E0x2D0x2C0x2B0x29 page 72page 97 0x2A Reserved0x28 GTCCR0x27 Reserved0x26 CLKPR0x25 Reserved 0x24 Reserved0x23 Reserved0x22 Reserved 0x21 WTCR0x20 Reserved0x1F Reserved0x1E0x1D0x1C0x1A EEARLEEDREECRReserved page 73page 76page 25 page 39 page 15page 15page 16 0x1B Reserved0x19 Reserved0x18 PORTB0x170x15 DDRBPCMSK 0x16 PINB0x14 IR00x13 Reserved0x120x10 ReservedReserved 0x11 Reserved0x0F Reserved0x0E Reserved0x0D0x0C0x0B0x0A0x090x080x070x060x050x040x030x020x010x00 ReservedReservedReservedReservedReservedACSRADMUXADCSRAADCHADCLADCSRBReservedReservedReserved – ACME – page 53page 53page 53page 57page 79, page 94 page 77page 91page 92page 93page 93 ADC Data Register High ByteADC Data Register Low Byte – ––– – ADTS2 ADTS1 ADTS0 page 94 159 2535G–AVR–01/07 元器件交易网www.cecb2b.com Note: 1.For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written.2.I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3.Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operation the specified bit, and can therefore be used on registers containing such Status Flags. TheCBI and SBI instructions work with registers 0x00 to 0x1F only. 160 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 Instruction Set Summary Mnemonics ADDADCADIWSUBSUBISBCSBCISBIWANDANDIORORIEORCOMNEGSBRCBRINCDECTSTCLRSERRJMPIJMPRCALLICALLRETRETICPSECPCPCCPISBRCSBRSSBICSBISBRBSBRBCBREQBRNEBRCSBRCCBRSHBRLOBRMIBRPLBRGEBRLTBRHSBRHCBRTSBRTCBRVSBRVCBRIEBRIDSBICBILSLLSRROL Rd,RrRd,RrRd,RrRd,KRr, bRr, bP, bP, bs, ks, k k k k k k k k k k k k k k k k k k kP,bP,bRdRdRdk Operands Rd, RrRd, RrRdl,KRd, RrRd, KRd, RrRd, KRdl,KRd, RrRd, KRd, RrRd, KRd, RrRdRdRd,KRd,KRdRdRdRdRdk Add two Registers Description Rd ← Rd + Rr OperationFlags Z,C,N,V,HZ,C,N,V,HZ,C,N,V,SZ,C,N,V,HZ,C,N,V,HZ,C,N,V,HZ,C,N,V,HZ,C,N,V,SZ,N,VZ,N,VZ,N,VZ,N,VZ,N,VZ,C,N,VZ,C,N,V,HZ,N,VZ,N,VZ,N,VZ,N,VZ,N,VZ,N,VNoneNoneNoneNoneNoneNoneINoneZ, N,V,C,HZ, N,V,C,HZ, N,V,C,HNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneZ,C,N,VZ,C,N,VZ,C,N,V #Clocks 11211112111111111111112233441/2/31 111/2/31/2/31/2/31/2/31/21/21/21/21/21/21/21/21/21/21/21/21/21/21/21/21/21/21/21/222111 ARITHMETIC AND LOGIC INSTRUCTIONS Add with Carry two RegistersAdd Immediate to WordSubtract two Registers Subtract Constant from Register Subtract with Carry two RegistersSubtract with Carry Constant from Reg.Subtract Immediate from WordLogical AND Registers Logical AND Register and ConstantLogical OR Registers Rd ← Rd + Rr + CRdh:Rdl ← Rdh:Rdl + KRd ← Rd - RrRd ← Rd - KRd ← Rd - Rr - CRd ← Rd - K - CRdh:Rdl ← Rdh:Rdl - KRd ← Rd • RrRd ← Rd • KRd ← Rd v Rr Logical OR Register and ConstantRd ← Rd v K Exclusive OR RegistersRd ← Rd ⊕ RrOne’s ComplementTwo’s ComplementSet Bit(s) in RegisterClear Bit(s) in RegisterIncrementDecrement Test for Zero or MinusClear RegisterSet RegisterRelative JumpIndirect Jump to (Z)Relative Subroutine Call Indirect Call to (Z)Subroutine ReturnInterrupt ReturnCompare, Skip if EqualCompare Compare with Carry Compare Register with ImmediateSkip if Bit in Register ClearedSkip if Bit in Register is SetSkip if Bit in I/O Register ClearedSkip if Bit in I/O Register is SetBranch if Status Flag SetBranch if Status Flag ClearedBranch if Equal Branch if Not EqualBranch if Carry SetBranch if Carry ClearedBranch if Same or Higher Branch if LowerBranch if MinusBranch if Plus Branch if Greater or Equal, SignedBranch if Less Than Zero, SignedBranch if Half Carry Flag SetBranch if Half Carry Flag ClearedBranch if T Flag SetBranch if T Flag ClearedBranch if Overflow Flag is SetBranch if Overflow Flag is ClearedBranch if Interrupt EnabledBranch if Interrupt DisabledSet Bit in I/O RegisterClear Bit in I/O RegisterLogical Shift LeftLogical Shift RightRotate Left Through Carry Rd ← 0xFF − RdRd ← 0x00 − RdRd ← Rd v KRd ← Rd • (0xFF - K)Rd ← Rd + 1Rd ← Rd − 1 Rd ← Rd • Rd Rd ← Rd ⊕ RdRd ← 0xFFPC ← PC + k + 1PC ← Z PC ← PC + k + 1PC ←ZPC ← STACKPC ← STACK if (Rd = Rr) PC ← PC + 2 or 3Rd − RrRd − Rr − CRd − K if (Rr(b)=0) PC ← PC + 2 or 3 if (Rr(b)=1) PC ← PC + 2 or 3if (P(b)=0) PC ← PC + 2 or 3 if (P(b)=1) PC ← PC + 2 or 3if (SREG(s) = 1) then PC←PC+k + 1if (SREG(s) = 0) then PC←PC+k + 1if (Z = 1) then PC ← PC + k + 1if (Z = 0) then PC ← PC + k + 1if (C = 1) then PC ← PC + k + 1if (C = 0) then PC ← PC + k + 1if (C = 0) then PC ← PC + k + 1if (C = 1) then PC ← PC + k + 1if (N = 1) then PC ← PC + k + 1if (N = 0) then PC ← PC + k + 1if (N ⊕ V= 0) then PC ← PC + k + 1if (N ⊕ V= 1) then PC ← PC + k + 1if (H = 1) then PC ← PC + k + 1if (H = 0) then PC ← PC + k + 1if (T = 1) then PC ← PC + k + 1if (T = 0) then PC ← PC + k + 1if (V = 1) then PC ← PC + k + 1if (V = 0) then PC ← PC + k + 1if ( I = 1) then PC ← PC + k + 1if ( I = 0) then PC ← PC + k + 1I/O(P,b) ←1I/O(P,b) ←0 Rd(n+1) ← Rd(n), Rd(0) ← 0Rd(n) ← Rd(n+1), Rd(7) ← 0Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) BRANCH INSTRUCTIONS BIT AND BIT-TEST INSTRUCTIONS 161 2535G–AVR–01/07 元器件交易网www.cecb2b.com Mnemonics RORASRSWAPBSETBCLRBSTBLDSECCLCSENCLNSEZCLZSEICLISESCLSSEVCLVSETCLTSEHCLH Operands RdRdRdssRr, bRd, b Arithmetic Shift RightSwap NibblesFlag SetFlag Clear Description Rotate Right Through Carry Operation Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)Rd(n) ← Rd(n+1), n=0..6 Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)SREG(s) ← 1SREG(s) ← 0 T ← Rr(b)Rd(b) ←TC ←1C ← 0 N ←1N ← 0 Z ←1Z ← 0 I ←1I ← 0 S ←1 Flags Z,C,N,VZ,C,N,VNoneSREG(s)SREG(s)TNoneCCNNZZIISSVVTTHHNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNone #Clocks 111111111111111111111111112222222222222222222222223331122111N/A Bit Store from Register to TBit load from T to RegisterSet CarryClear CarrySet Negative FlagClear Negative FlagSet Zero FlagClear Zero FlagGlobal Interrupt EnableGlobal Interrupt DisableSet Signed Test FlagClear Signed Test Flag S ← 0 Set Twos Complement Overflow.V ←1Clear Twos Complement OverflowSet T in SREGClear T in SREG V ← 0 T ←1 T ← 0 DATA TRANSFER INSTRUCTIONSMOVMOVWLDILDLDLDLDLDLDLDDLDLDLDLDDLDSSTSTSTSTSTSTSTDSTSTSTSTDSTSLPMLPMLPMSPMINOUTPUSHPOPNOPSLEEPWDR BREAK Rd, PP, RrRrRdRd, ZRd, Z+Rd, RrRd, RrRd, KRd, XRd, X+Rd, - XRd, YRd, Y+Rd, - YRd,Y+qRd, ZRd, Z+Rd, -ZRd, Z+qRd, kX, RrX+, Rr- X, RrY, RrY+, Rr- Y, RrY+q,RrZ, RrZ+, Rr-Z, RrZ+q,Rrk, Rr Set Half Carry Flag in SREG H ←1Clear Half Carry Flag in SREGH ← 0 Move Between RegistersCopy Register WordLoad ImmediateLoad Indirect Rd ← Rr Rd+1:Rd ← Rr+1:Rr Rd ←K Rd ← (X) Load Indirect and Post-Inc. Rd ← (X), X ← X + 1Load Indirect and Pre-Dec.Load Indirect X ← X - 1, Rd ← (X) Rd ← (Y) Rd ← (Y), Y ← Y + 1Y ← Y - 1, Rd ← (Y)Rd ← (Y + q)Rd ← (Z) Rd ← (Z), Z ← Z+1Z ← Z - 1, Rd ← (Z)Rd ← (Z + q)Rd ← (k)(X) ← Rr (X) ← Rr, X ← X + 1X ← X - 1, (X) ← Rr(Y) ← Rr (Y) ← Rr, Y ← Y + 1Y ← Y - 1, (Y) ← Rr(Y + q) ← Rr(Z) ← Rr (Z) ← Rr, Z ← Z + 1Z ← Z - 1, (Z) ← Rr(Z + q) ← Rr(k) ← RrR0 ← (Z)Rd ← (Z) Rd ← (Z), Z ← Z+1(z) ← R1:R0Rd ←PP ← RrSTACK ← RrRd ← STACK Load Indirect and Post-Inc.Load Indirect and Pre-Dec.Load Indirect with DisplacementLoad Indirect Load Indirect and Post-Inc.Load Indirect and Pre-Dec.Load Indirect with DisplacementLoad Direct from SRAMStore Indirect Store Indirect and Post-Inc.Store Indirect and Pre-Dec.Store Indirect Store Indirect and Post-Inc.Store Indirect and Pre-Dec.Store Indirect with DisplacementStore Indirect Store Indirect and Post-Inc.Store Indirect and Pre-Dec.Store Indirect with DisplacementStore Direct to SRAMLoad Program MemoryLoad Program Memory Load Program Memory and Post-IncStore Program MemoryIn PortOut Port Push Register on StackPop Register from StackNo OperationSleep Watchdog Reset Break MCU CONTROL INSTRUCTIONS (see specific descr. for Sleep function)(see specific descr. for WDR/Timer)For On-chip Debug Only NoneNoneNone 162 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 Ordering Information Speed (MHz)(3) Power Supply Ordering CodeATtiny13V-10PIATtiny13V-10PU(2)ATtiny13V-10SIATtiny13V-10SU(2)ATtiny13V-10SSIATtiny13V-10SSU(2)IATtiny13V-10MU(2)ATtiny13-20PIATtiny13-20PU(2)ATtiny13-20SIATtiny13-20SU(2)ATtiny13-20SSIATtiny13-20SSU(2)ATtiny13-20MU(2) Package(1)8P38P38S28S2S8S1S8S120M18P38P38S28S2S8S1S8S120M1 Operation Range 101.8 - 5.5 Industrial(-40°C to 85°C) 202.7 - 5.5 Industrial(-40°C to 85°C) Notes: 1.This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2.Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS direc-tive). Also Halide free and fully Green 3.For Speed vs. VCC, see “Maximum Speed vs. VCC” on page 123. Package Type 8P38S2S8S120M1 8-lead, 0.300\" Wide, Plastic Dual Inline Package (PDIP)8-lead, 0.209\" Wide, Plastic Small Outline Package (EIAJ SOIC)8-lead, 0.150\" Wide, Plastic Gull-Wing Small Outline (JEDEC SOIC) 20-pad, 4 x 4 x 0.8 mm Body, Lead Pitch 0.50 mm, Micro Lead Frame Package (MLF) 163 2535G–AVR–01/07 元器件交易网www.cecb2b.com Packaging Information 8P3 1EE1NTop ViewceAEnd ViewCOMMON DIMENSIONS(Unit of Measure = inches)DD1eA2ASYMBOLMINNOMMAXNOTEAA2bb2b3cD0.1150.0140.0450.0300.0080.3550.0050.3000.2400.3100.2500.100 BSC0.300 BSC0.1150.1300.1300.0180.0600.0390.0100.3650.2100.1950.0220.0700.0450.0140.4000.3250.280256633434b2b34 PLCSLD1EE1eeALbSide View0.1502Notes:1.This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.2.Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.3.D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.4.E and eA measured with the leads constrained to be perpendicular to datum.5.Pointed or rounded lead tips are preferred to ease insertion.6.b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).01/09/022325 Orchard ParkwaySan Jose, CA 95131TITLE8P3, 8-lead, 0.300\" Wide Body, Plastic Dual In-line Package (PDIP)DRAWING NO.8P3REV. BR1 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 8S2 C1EE1LNTOP VIEWθEND VIEWeASYMBOLbCOMMON DIMENSIONS(Unit of Measure = mm)MINNOMMAXNOTEA1A 1.70 2.16 A1 0.05 b 0.35 D 5.13 E1 5.18 0.25 0.48 5.35 5.40 2, 35C 0.15 0.35 5DE 7.70 8.26 SIDE VIEWL 0.51 0.85 θ e 0° 8°4 1.27 BSC Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. 2. Mismatch of the upper and lower dies and resin burrs are not included. 3. It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded. 4. Determines the true geometric position. 5. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm.4/7/062325 Orchard ParkwaySan Jose, CA 95131TITLE8S2, 8-lead, 0.209\" Body, Plastic Small Outline Package (EIAJ)DRAWING NO.8S2REV. DR165 2535G–AVR–01/07 元器件交易网www.cecb2b.com S8S1 321HNTop VieweBADSide ViewSYMBOLACOMMON DIMENSIONS(Unit of Measure = mm)MIN–––––NOM–––––1.27 BSC––––6.201.27MAX1.750.510.255.004.00NOTEA2BCCDELEeHLEnd ViewNote: This drawing is for general information only. Refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums, etc.10/10/01 2325 Orchard Parkway San Jose, CA 95131TITLE8S1, 8-lead (0.150\" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC)DRAWING NO.8S1REV. AR166 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 20M1 D1Pin 1 ID23ESIDE VIEWTOP VIEWA2D2 A1Pin #1 Notch(0.20 R) 23A10.08CE2SYMBOLCOMMON DIMENSIONS(Unit of Measure = mm)MINNOMMAXNOTEbA 0.70 0.75 0.80A1 – 0.01 0.05LeBOTTOM VIEWA2 0.20 REFb 0.18 0.23 0.30 D 4.00 BSCD2 2.45 2.60 2.75E 4.00 BSCE2 2.45 2.60 2.75e0.50 BSCNote: Reference JEDEC Standard MO-220, Fig. 1 (SAW Singulation) WGGD-5.L 0.35 0.40 0.55 10/27/04TITLE 2325 Orchard Parkway20M1, 20-pad, 4 x 4 x 0.8 mm Body, Lead Pitch 0.50 mm, San Jose, CA 95131 2.6 mm Exposed Pad, Micro Lead Frame Package (MLF) DRAWING NO.20M1REV. AR167 2535G–AVR–01/07 元器件交易网www.cecb2b.com Errata ATtiny13 Rev. D The revision letter in this section refers to the revision of the ATtiny13 device.•EEPROM can not be written below 1.9 Volt1.EEPROM can not be written below 1.9 Volt Writing the EEPROM at VCC below 1.9 volts might fail.Problem Fix/Workaround Do not write the EEPROM when VCC is below 1.9 volts. ATtiny13 Rev. B ••••••Wrong values read after Erase Only operation High Voltage Serial Programming Flash, EEPROM, Fuse and Lock Bits may failDevice may lock for further programming debugWIRE communication not blocked by lock-bitsWatchdog Timer Interrupt disabled EEPROM can not be written below 1.9 Volt 1.Wrong values read after Erase Only operation At supply voltages below 2.7 V, an EEPROM location that is erased by the EraseOnly operation may read as programmed (0x00).Problem Fix/Workaround If it is necessary to read an EEPROM location after Erase Only, use an Atomic Writeoperation with 0xFF as data in order to erase a location. In any case, the Write Onlyoperation can be used as intended. Thus no special considerations are needed aslong as the erased location is not read before it is programmed. 2.High Voltage Serial Programming Flash, EEPROM, Fuse and Lock Bits may fail Writing to any of these locations and bits may in some occasions fail.Problem Fix/Workaround After a writing has been initiated, always observe the RDY/BSY signal. If the writingshould fail, rewrite until the RDY/BSY verifies a correct writing. This will be fixed inrevision D. 3.Device may lock for further programming Special combinations of fuse bits will lock the device for further programming effec-tively turning it into an OTP device. The following combinations of settings/fuse bitswill cause this effect:– 128 kHz internal oscillator (CKSEL[1..0] = 11), shortest start-up time(SUT[1..0] = 00), Debugwire enabled (DWEN = 0) or Reset disabledRSTDISBL = 0. 9.6 MHz internal oscillator (CKSEL[1..0] = 10), shortest start-up time(SUT[1..0] = 00), Debugwire enabled (DWEN = 0) or Reset disabledRSTDISBL = 0. 4.8 MHz internal oscillator (CKSEL[1..0] = 01), shortest start-up time(SUT[1..0] = 00), Debugwire enabled (DWEN = 0) or Reset disabledRSTDISBL = 0. – – Problem fix/ Workaround Avoid the above fuse combinations. Selecting longer start-up time will eliminate theproblem. 168 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 4.debugWIRE communication not blocked by lock-bits When debugWIRE on-chip debug is enabled (DWEN = 0), the contents of programmemory and EEPROM data memory can be read even if the lock-bits are set toblock further reading of the device.Problem fix/ Workaround Do not ship products with on-chip debug of the tiny13 enabled.5.Watchdog Timer Interrupt disabled If the watchdog timer interrupt flag is not cleared before a new timeout occurs, thewatchdog will be disabled, and the interrupt flag will automatically be cleared. This isonly applicable in interrupt only mode. If the Watchdog is configured to reset thedevice in the watchdog time-out following an interrupt, the device works correctly.Problem fix / Workaround Make sure there is enough time to always service the first timeout event before anew watchdog timeout occurs. This is done by selecting a long enough time-outperiod. 6.EEPROM can not be written below 1.9 Volt Writing the EEPROM at VCC below 1.9 volts might fail.Problem Fix/Workaround Do not write the EEPROM when VCC is below 1.9 volts. ATtiny13 Rev. A Revision A has not been sampled. 169 2535G–AVR–01/07 元器件交易网www.cecb2b.com Datasheet Revision History Changes from Rev. 2535F-04/06 to Rev. 2535G-01/07 Please note that the referring page numbers in this section are referring to this docu-ment. The referring revision in this section are referring to the document revision. 1.2.3.4.5.6.7.8.9.Removed Preliminary. Updated Table 12 on page 31, Table 16 on page 39,Table 51 on page 111.Removed Note from Table 15 on page 35. Updated “Bit 6 – ACBG: Analog Comparator Bandgap Select” on page 78.Updated “Prescaling and Conversion Timing” on page 83.Updated Figure 56 on page 111. Updated “DC Characteristics” on page 120.Updated “Ordering Information” on page 163.Updated “Packaging Information” on page 1. Changes from Rev. 2535E-10/04 to Rev. 2535F-04/06Changes from Rev. 2535D-04/04 to Rev. 2535E-10/04 1.Revision not published. 1.2.3.2.4.5.6.7.8.9.10.11.12.Bits EEMWE/EEWE changed to EEMPE/EEPE in document.Updated “Pinout ATtiny13” on page 2. Updated “Write Fuse Low Bits” in Table 55 on page 117, Table 57 on page122. Added “Pin Change Interrupt Timing” on page . Updated “General Interrupt Mask Register – GIMSK” on page 56.Updated “Pin Change Mask Register – PCMSK” on page 57. Updated item 4 in “Serial Programming Algorithm” on page 108. Updated “Enter High-voltage Serial Programming Mode” on page 113.Updated “DC Characteristics” on page 120. Updated “Typical Characteristics” on page 125.Updated “Ordering Information” on page 163.Updated “Packaging Information” on page 1.Updated “Errata” on page 168. Changes from Rev. 2535C-02/04 to Rev. 2535D-04/04 1. 2.3.4. Maximum Speed Grades changed- 12MHz to 10MHz- 24MHz to 20MHz Updated “Serial Programming Instruction Set” on page 110.Updated “Maximum Speed vs. VCC” on page 123Updated “Ordering Information” on page 163 Changes from Rev. 2535B-01/04 to Rev. 2535C-02/04 1.2.3.C-code examples updated to use legal IAR syntax. Replaced occurrences of WDIF with WDTIF and WDIE with WDTIE.Updated “Stack Pointer” on page 9. 170 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 4.5.6.7.8.9.10.11. Updated “Calibrated Internal RC Oscillator” on page 23. Updated “Oscillator Calibration Register – OSCCAL” on page 23.Updated typo in introduction on “Watchdog Timer” on page 36.Updated “ADC Conversion Time” on page 85.Updated “Serial Downloading” on page 107. Updated “Electrical Characteristics” on page 120.Updated “Ordering Information” on page 163.Removed rev. C from “Errata” on page 168. Changes from Rev. 2535A-06/03 to Rev. 2535B-01/04 1.2.3.4.5.6. 7.8.9.10.11.12.13.14. Updated Figure 2 on page 3. Updated Table 12 on page 31, Table 17 on page 41, Table 37 on page 92and Table 57 on page 122. Updated “Calibrated Internal RC Oscillator” on page 23.Updated the whole “Watchdog Timer” on page 36. Updated Figure on page 107 and Figure 57 on page 112. Updated registers “MCU Control Register – MCUCR” on page 51,“Timer/Counter Control Register B – TCCR0B” on page 72 and “DigitalInput Disable Register 0 – DIDR0” on page 79. Updated Absolute Maximum Ratings and DC Characteristics in “ElectricalCharacteristics” on page 120. Added “Maximum Speed vs. VCC” on page 123Updated “ADC Characteristics” on page 124.Updated “Typical Characteristics” on page 125.Updated “Ordering Information” on page 163.Updated “Packaging Information” on page 1.Updated “Errata” on page 168. Changed instances of EEAR to EEARL. 171 2535G–AVR–01/07 元器件交易网www.cecb2b.com 172 ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 Table of Contents Features................................................................................................ 1Pin Configurations............................................................................... 2Overview............................................................................................... 2 Block Diagram...................................................................................................... 3Pin Descriptions.................................................................................................... 4 About Code Examples......................................................................... 4AVR CPU Core..................................................................................... 5 Introduction........................................................................................................... 5Architectural Overview.......................................................................................... 5ALU – Arithmetic Logic Unit.................................................................................. 6Status Register..................................................................................................... 7General Purpose Register File............................................................................. 8Stack Pointer........................................................................................................ 9Instruction Execution Timing............................................................................... 10Reset and Interrupt Handling.............................................................................. 10 AVR Memories................................................................................... 13 In-System Re-programmable Flash Program Memory....................................... 13SRAM Data Memory........................................................................................... 14EEPROM Data Memory...................................................................................... 15I/O Memory......................................................................................................... 20 System Clock and Clock Options.................................................... 21 Clock Systems and their Distribution.................................................................. 21Clock Sources..................................................................................................... 22Default Clock Source.......................................................................................... 22Calibrated Internal RC Oscillator........................................................................ 23External Clock..................................................................................................... 24128 kHz Internal Oscillator.................................................................................. 25System Clock Prescaler...................................................................................... 25 Power Management and Sleep Modes............................................. 27 Idle Mode............................................................................................................ 28ADC Noise Reduction Mode............................................................................... 28Power-down Mode.............................................................................................. 28Minimizing Power Consumption......................................................................... 29 System Control and Reset................................................................ 30 Internal Voltage Reference................................................................................. 35Watchdog Timer................................................................................................. 36 Interrupts............................................................................................ 42 i 2535G–AVR–01/07 元器件交易网www.cecb2b.com Interrupt Vectors in ATtiny13.............................................................................. 42 I/O Ports.............................................................................................. 43 Introduction......................................................................................................... 43Ports as General Digital I/O................................................................................ 44Alternate Port Functions..................................................................................... 48Register Description for I/O-Ports....................................................................... 53 External Interrupts............................................................................. Pin Change Interrupt Timing............................................................................... External Interrupt registers................................................................................. 55 8-bit Timer/Counter0 with PWM........................................................ 58 Overview............................................................................................................. 58Timer/Counter Clock Sources............................................................................. 59Counter Unit........................................................................................................ 59Output Compare Unit.......................................................................................... 60Compare Match Output Unit............................................................................... 62Modes of Operation............................................................................................ 63Timer/Counter Timing Diagrams......................................................................... 678-bit Timer/Counter Register Description........................................................... 69 Timer/Counter Prescaler................................................................... 75Analog Comparator........................................................................... 77 Analog Comparator Multiplexed Input................................................................ 79 Analog to Digital Converter.............................................................. 80 Features.............................................................................................................. 80Operation............................................................................................................ 81Starting a Conversion......................................................................................... 82Prescaling and Conversion Timing..................................................................... 83Changing Channel or Reference Selection........................................................ 86ADC Noise Canceler........................................................................................... 87ADC Conversion Result...................................................................................... 91 debugWIRE On-chip Debug System................................................ 96 Features.............................................................................................................. 96Overview............................................................................................................. 96Physical Interface............................................................................................... 96Software Break Points........................................................................................ 97Limitations of debugWIRE.................................................................................. 97debugWIRE Related Register in I/O Memory..................................................... 97 Self-Programming the Flash............................................................. 98 Addressing the Flash During Self-Programming................................................ 99 ii ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 Memory Programming..................................................................... 103 Program And Data Memory Lock Bits.............................................................. 103Fuse Bytes........................................................................................................ 104Signature Bytes................................................................................................ 106Calibration Byte................................................................................................ 106Page Size......................................................................................................... 106Serial Downloading........................................................................................... 107High-voltage Serial Programming..................................................................... 112High-voltage Serial Programming Algorithm..................................................... 113High-voltage Serial Programming Characteristics............................................ 119 Electrical Characteristics................................................................ 120 Absolute Maximum Ratings*............................................................................. 120DC Characteristics............................................................................................ 120External Clock Drive Waveforms...................................................................... 122External Clock Drive......................................................................................... 122Maximum Speed vs. VCC.................................................................................. 123ADC Characteristics......................................................................................... 124 Typical Characteristics................................................................... 125 Active Supply Current....................................................................................... 125Idle Supply Current........................................................................................... 128Power-Down Supply Current............................................................................ 131Pin Pull-up........................................................................................................ 132Pin Driver Strength........................................................................................... 134Pin Thresholds and Hysteresis......................................................................... 143BOD Thresholds and Analog Comparator Offset............................................. 148Internal Oscillator Speed.................................................................................. 151Current Consumption of Peripheral Units......................................................... 155Current Consumption in Reset and Reset Pulse width..................................... 157 Register Summary........................................................................... 159Instruction Set Summary................................................................ 161Ordering Information....................................................................... 163Packaging Information.................................................................... 1 8P3................................................................................................................... 18S2................................................................................................................... 165S8S1................................................................................................................. 16620M1................................................................................................................. 167 Errata................................................................................................ 168 ATtiny13 Rev. D................................................................................................ 168ATtiny13 Rev. B................................................................................................ 168 iii 2535G–AVR–01/07 元器件交易网www.cecb2b.com ATtiny13 Rev. A................................................................................................ 169 Datasheet Revision History............................................................ 170 Changes from Rev. 2535F-04/06 to Rev. 2535G-01/07................................... 170Changes from Rev. 2535E-10/04 to Rev. 2535F-04/06................................... 170Changes from Rev. 2535D-04/04 to Rev. 2535E-10/04................................... 170Changes from Rev. 2535C-02/04 to Rev. 2535D-04/04................................... 170Changes from Rev. 2535B-01/04 to Rev. 2535C-02/04................................... 170Changes from Rev. 2535A-06/03 to Rev. 2535B-01/04................................... 171 Table of Contents................................................................................. i iv ATtiny13 2535G–AVR–01/07 元器件交易网www.cecb2b.com Atmel Corporation 2325 Orchard ParkwaySan Jose, CA 95131, USATel: 1(408) 441-0311Fax: 1(408) 487-2600 Atmel Operations Memory 2325 Orchard ParkwaySan Jose, CA 95131, USATel: 1(408) 441-0311Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2Postfach 3535 74025 Heilbronn, GermanyTel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. 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